cpu/allwinner/a10/clock.h: Add missing bracket
Code checked manually Change-Id: I92f0b5d47c60c259171c4db90fb5003f4eb8580b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
parent
9c07722555
commit
80d11b2d58
|
@ -51,7 +51,7 @@
|
||||||
#define APB1_CLK_SRC_32K (2 << 24)
|
#define APB1_CLK_SRC_32K (2 << 24)
|
||||||
#define APB1_RAT_N_MASK (3 << 16)
|
#define APB1_RAT_N_MASK (3 << 16)
|
||||||
#define APB1_RAT_N(m) (((m) & 0x3) << 16)
|
#define APB1_RAT_N(m) (((m) & 0x3) << 16)
|
||||||
#define APB1_RAT_M_MASK 0x1f << 0)
|
#define APB1_RAT_M_MASK (0x1f << 0)
|
||||||
#define APB1_RAT_M(n) (((n) & 0x1f) << 0)
|
#define APB1_RAT_M(n) (((n) & 0x1f) << 0)
|
||||||
|
|
||||||
/* PLL5_CFG values */
|
/* PLL5_CFG values */
|
||||||
|
|
Loading…
Reference in New Issue