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mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblock 

The SPI ROM REQ/GNT pins are used in systems where the EC and the APU
share one flash chip to make sure that not both devices will try to
access the flash at the same time. The firmware running before the x86
cores are released from reset has likely already done this, but do it
again in bootblock just to be sure. The KBRST_L pin can be used to reset
the APU from the EC.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-02-13 22:20:42 +01:00
parent 72236b475f
commit 80ddd29adb
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/amd/chausie/early_gpio.c
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@ -24,6 +24,12 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
/* TPM IRQ */
PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW),
/* SPI_ROM_REQ */
PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE),
/* SPI_ROM_GNT */
PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE),
/* KBRST_L */
PAD_NF(GPIO_21, KBRST_L, PULL_NONE),
/* Deassert PCIe Reset lines */
/* PCIE_RST0_L */