Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-60
Creator: Li-Ta Lo <ollie@lanl.gov> More Via EPIA more via epia stuff, including the trival but fatal bug in auto.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
parent
f642a4795a
commit
80e3d96d0a
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@ -126,20 +126,18 @@ config chip.h
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chip northbridge/via/vt8601
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device pci_domain 0 on
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device pci 0.0 on
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device pci 0.0 on end # Northbridge
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device pci 0.1 on # AGP bridge
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# chip drivers/pci/onboard # Integrated VGA
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# device pci 0.0 on end
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# register "rom_adress" = "0xfff80000"
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# end
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end
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chip southbridge/via/vt8231
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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register "enable_com_ports" = "1"
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register "enable_keyboard" = "0"
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register "enable_nvram" = "1"
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device pci 11.0 on # Southbridge
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device pci 11.1 on end # Ide
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device pci 11.2 off end # Usb
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device pci 11.3 off end # Usb
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device pci 11.4 off end # ACPI
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device pci 11.5 off end # Audio
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device pci 11.6 on # Com
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device pci 11.0 on # Southbrdge
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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@ -164,6 +162,8 @@ chip northbridge/via/vt8601
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irq 0x70 = 1
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irq 0x72 = 12
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end
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register "com1" = "{1}"
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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@ -172,14 +172,17 @@ chip northbridge/via/vt8601
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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register "com1" = "{1}"
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end
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end
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device pci 11.1 on end # Ide
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device pci 11.2 off end # Usb port 0-1
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device pci 11.3 off end # Usb port 2-3
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device pci 11.4 off end # ACPI
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device pci 11.5 off end # AC97 Audio
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device pci 11.6 on end # AC97 Modem
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device pci 12.0 on end # Ethernet
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end
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end
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end
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end
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chip cpu/via/model_centaur
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end
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end
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@ -1,3 +1,10 @@
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_CHIP_NAME
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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@ -40,6 +47,18 @@ uses MAXIMUM_CONSOLE_LOGLEVEL
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=19200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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default CONFIG_CHIP_NAME=1
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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@ -2,9 +2,6 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#if 0
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#include <cpu/x86/lapic.h>
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#endif
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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@ -21,7 +18,7 @@
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void udelay(int usecs)
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{
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int i;
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for(i = 0; i < usecs; i++)
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for (i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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@ -30,18 +27,8 @@ void udelay(int usecs)
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#include "debug.c"
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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static void memreset_setup(void)
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{
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}
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/*
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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unsigned char c;
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@ -49,8 +36,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return c;
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}
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#include "northbridge/via/vt8601/raminit.c"
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/*
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#include "sdram/generic_sdram.c"
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@ -66,6 +51,7 @@ static void enable_mainboard_devices(void)
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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#if 0
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@ -87,9 +73,9 @@ static void enable_mainboard_devices(void)
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static void enable_shadow_ram(void)
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{
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device_t dev = 0; /* no need to look up 0:0.0 */
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device_t dev = 0;
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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@ -113,8 +99,8 @@ static void main(unsigned long bist)
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enable_mainboard_devices();
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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@ -29,8 +29,6 @@ static void northbridge_init(device_t dev)
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pci_write_config8(dev, 0x76, 0x52);
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}
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static struct device_operations northbridge_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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@ -46,8 +44,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
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.device = 0x0601, /* 0x8601 is the AGP bridge? */
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};
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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@ -53,8 +53,8 @@ void dimms_read(unsigned long x)
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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y = * (volatile unsigned long *) eax;
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for (c = 0; c < 6; c++) {
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y = *(volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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}
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@ -63,14 +63,12 @@ void dimms_write(int x)
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{
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uint8_t c;
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unsigned long eax = x;
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for(c = 0; c < 6; c++) {
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for (c = 0; c < 6; c++) {
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*(volatile unsigned long *) eax = 0;
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eax += 0x10000000;
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}
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}
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#ifdef DEBUG_SETNORTHB
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void setnorthb(device_t north, uint8_t reg, uint8_t val)
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{
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@ -85,15 +83,14 @@ void setnorthb(device_t north, uint8_t reg, uint8_t val)
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#define setnorthb pci_write_config8
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#endif
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void
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dumpnorth(device_t north)
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void dumpnorth(device_t north)
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{
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unsigned int r, c;
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for(r = 0; ; r += 16) {
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for (r = 0;; r += 16) {
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print_debug_hex8(r);
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print_debug(":");
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for(c = 0; c < 16; c++) {
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print_debug_hex8(pci_read_config8(north, r+c));
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for (c = 0; c < 16; c++) {
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print_debug_hex8(pci_read_config8(north, r + c));
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print_debug(" ");
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}
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print_debug("\r\n");
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@ -104,12 +101,10 @@ dumpnorth(device_t north)
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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device_t north = (device_t) 0;
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device_t north = (device_t) PCI_DEV(0, 0, 0);
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uint8_t c, r;
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print_err("vt8601 init starting\r\n");
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north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
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north = 0;
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print_debug_hex32(north);
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print_debug(" is the north\n");
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print_debug_hex16(pci_read_config16(north, 0));
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@ -120,72 +115,75 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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/* All we are doing now is setting initial known-good values that will
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* be revised later as we read SPD
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*/
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// memory clk enable. We are not using ECC
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pci_write_config8(north,0x78, 0x01);
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pci_write_config8(north, 0x78, 0x01);
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print_debug_hex8(pci_read_config8(north, 0x78));
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// dram control, see the book.
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#if DIMM_PC133
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pci_write_config8(north,0x68, 0x52);
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pci_write_config8(north, 0x68, 0x52);
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#else
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pci_write_config8(north,0x68, 0x42);
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pci_write_config8(north, 0x68, 0x42);
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#endif
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// dram control, see the book.
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pci_write_config8(north,0x6B, 0x0c);
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pci_write_config8(north, 0x6B, 0x0c);
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// Initial setting, 256MB in each bank, will be rewritten later.
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pci_write_config8(north,0x5A, 0x20);
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pci_write_config8(north, 0x5A, 0x20);
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print_debug_hex8(pci_read_config8(north, 0x5a));
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pci_write_config8(north,0x5B, 0x40);
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pci_write_config8(north,0x5C, 0x60);
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pci_write_config8(north,0x5D, 0x80);
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pci_write_config8(north,0x5E, 0xA0);
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pci_write_config8(north,0x5F, 0xC0);
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pci_write_config8(north, 0x5B, 0x40);
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pci_write_config8(north, 0x5C, 0x60);
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pci_write_config8(north, 0x5D, 0x80);
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pci_write_config8(north, 0x5E, 0xA0);
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pci_write_config8(north, 0x5F, 0xC0);
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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pci_write_config8(north,0x56, 0xC0);
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pci_write_config8(north,0x57, 0xC0);
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pci_write_config8(north, 0x56, 0xC0);
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pci_write_config8(north, 0x57, 0xC0);
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// SDRAM in all banks
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pci_write_config8(north,0x60, 0x3F);
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pci_write_config8(north, 0x60, 0x3F);
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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#if DIMM_CL2
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pci_write_config8(north,0x64, 0xd4);
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pci_write_config8(north,0x65, 0xd4);
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pci_write_config8(north,0x66, 0xd4);
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pci_write_config8(north, 0x64, 0xd4);
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pci_write_config8(north, 0x65, 0xd4);
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pci_write_config8(north, 0x66, 0xd4);
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#else // CL=3
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pci_write_config8(north,0x64, 0xe4);
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pci_write_config8(north,0x65, 0xe4);
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pci_write_config8(north,0x66, 0xe4);
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pci_write_config8(north, 0x64, 0xe4);
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pci_write_config8(north, 0x65, 0xe4);
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pci_write_config8(north, 0x66, 0xe4);
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#endif
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// dram frequency select.
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// enable 4K pages for 64M dram.
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#if DIMM_PC133
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pci_write_config8(north,0x69, 0x3c);
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pci_write_config8(north, 0x69, 0x3c);
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#else
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pci_write_config8(north,0x69, 0xac);
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pci_write_config8(north, 0x69, 0xac);
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#endif
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/* IMPORTANT -- disable refresh counter */
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// refresh counter, disabled.
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pci_write_config8(north,0x6A, 0x00);
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pci_write_config8(north, 0x6A, 0x00);
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// clkenable configuration. kevinh FIXME - add precharge
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pci_write_config8(north,0x6C, 0x00);
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pci_write_config8(north, 0x6C, 0x00);
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// dram read latch delay of 1 ns, MD drive 8 mA,
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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pci_write_config8(north,0x6D, 0x7f);
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pci_write_config8(north, 0x6D, 0x7f);
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}
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/* slot is the dram slot. Return size of side0 in lower 16-bit,
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* side1 in upper 16-bit, in units of 8MB */
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static unsigned long
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spd_module_size(unsigned char slot)
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static unsigned long spd_module_size(unsigned char slot)
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{
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/* for all the DRAMS, see if they are there and get the size of each
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* module. This is just a very early first cut at sizing.
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@ -195,6 +193,7 @@ spd_module_size(unsigned char slot)
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unsigned int value = 0;
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/* unsigned int module = ((0x50 + slot) << 1) + 1; */
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unsigned int module = 0x50 + slot;
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/* is the module there? if byte 2 is not 4, then we'll assume it
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* is useless.
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*/
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@ -207,9 +206,11 @@ spd_module_size(unsigned char slot)
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print_info(" is SDRAM ");
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banks = smbus_read_byte(module, 17);
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/* we're going to assume symmetric banks. Sorry. */
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cols = smbus_read_byte(module, 4) & 0xf;
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rows = smbus_read_byte(module, 3) & 0xf;
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/* grand total. You have rows+cols addressing, * times of banks, times
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* width of data in bytes */
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/* Width is assumed to be 64 bits == 8 bytes */
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@ -229,10 +230,8 @@ spd_module_size(unsigned char slot)
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}
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static int
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spd_num_chips(unsigned char slot)
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static int spd_num_chips(unsigned char slot)
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{
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/* unsigned int module = ((0x50 + slot) << 1) + 1; */
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unsigned int module = 0x50 + slot;
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unsigned int width;
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@ -249,10 +248,10 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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unsigned char timing = 0xe4;
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/* read Trp */
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val = smbus_read_byte(0x50, 27);
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if (val < 2*T133)
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if (val < 2 * T133)
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Trp = 1;
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val = smbus_read_byte(0x50, 30);
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if (val < 5*T133)
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if (val < 5 * T133)
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Tras = 0;
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val = smbus_read_byte(0x50, 18);
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if (val < 8)
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@ -262,7 +261,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
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print_debug_hex8(val); print_debug(" is the computed timing\n");
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print_debug_hex8(val);
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print_debug(" is the computed timing\n");
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/* don't set it. Experience shows that this screwy chipset should just
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* be run with the most conservative timing.
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* pci_write_config8(0, 0x64, val);
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@ -274,8 +274,8 @@ static void set_ma_mapping(device_t north, int slot, int type)
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unsigned char reg, val;
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int shift;
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reg = 0x58 + slot/2;
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if (slot%2 >= 1)
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reg = 0x58 + slot / 2;
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if (slot % 2 >= 1)
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shift = 0;
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else
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shift = 4;
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@ -295,29 +295,30 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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};
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device_t north = 0;
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uint32_t size, base, slot, ma;
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/* begin to initialize*/
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/* begin to initialize */
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// I forget why we need this, but we do
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dimms_write(0xa55a5aa5);
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|
||||
/* set NOP*/
|
||||
pci_write_config8(north,0x6C, 0x01);
|
||||
/* set NOP */
|
||||
pci_write_config8(north, 0x6C, 0x01);
|
||||
print_debug("NOP\r\n");
|
||||
/* wait 200us*/
|
||||
/* wait 200us */
|
||||
// You need to do the memory reference. That causes the nop cycle.
|
||||
dimms_read(0);
|
||||
udelay(400);
|
||||
print_debug("PRECHARGE\r\n");
|
||||
/* set precharge */
|
||||
pci_write_config8(north,0x6C, 0x02);
|
||||
pci_write_config8(north, 0x6C, 0x02);
|
||||
print_debug("DUMMY READS\r\n");
|
||||
/* dummy reads*/
|
||||
/* dummy reads */
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_debug("CBR\r\n");
|
||||
/* set CBR*/
|
||||
pci_write_config8(north,0x6C, 0x04);
|
||||
/* set CBR */
|
||||
pci_write_config8(north, 0x6C, 0x04);
|
||||
|
||||
/* do 8 reads and wait >100us between each - from via*/
|
||||
/* do 8 reads and wait >100us between each - from via */
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
|
|
@ -335,8 +336,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_debug("MRS\r\n");
|
||||
/* set MRS*/
|
||||
pci_write_config8(north,0x6c, 0x03);
|
||||
/* set MRS */
|
||||
pci_write_config8(north, 0x6c, 0x03);
|
||||
#if DIMM_CL2
|
||||
dimms_read(0x150);
|
||||
#else // CL=3
|
||||
|
|
@ -345,7 +346,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
udelay(200);
|
||||
print_debug("NORMAL\r\n");
|
||||
/* set to normal mode */
|
||||
pci_write_config8(north,0x6C, 0x08);
|
||||
pci_write_config8(north, 0x6C, 0x08);
|
||||
|
||||
dimms_write(0x55aa55aa);
|
||||
dimms_read(0);
|
||||
|
|
@ -353,25 +354,25 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
print_debug("set ref. rate\r\n");
|
||||
// Set the refresh rate.
|
||||
#if DIMM_PC133
|
||||
pci_write_config8(north,0x6A, 0x86);
|
||||
pci_write_config8(north, 0x6A, 0x86);
|
||||
#else
|
||||
pci_write_config8(north,0x6A, 0x65);
|
||||
pci_write_config8(north, 0x6A, 0x65);
|
||||
#endif
|
||||
print_debug("enable multi-page open\r\n");
|
||||
// enable multi-page open
|
||||
pci_write_config8(north,0x6B, 0x0d);
|
||||
pci_write_config8(north, 0x6B, 0x0d);
|
||||
|
||||
base = 0;
|
||||
for(slot = 0; slot < 4; slot++) {
|
||||
for (slot = 0; slot < 4; slot++) {
|
||||
size = spd_module_size(slot);
|
||||
/* side 0 */
|
||||
base += size & 0xffff;
|
||||
pci_write_config8(north, ramregs[2*slot], base);
|
||||
pci_write_config8(north, ramregs[2 * slot], base);
|
||||
/* side 1 */
|
||||
base += size >> 16;
|
||||
if (base > 0xff)
|
||||
base = 0xff;
|
||||
pci_write_config8(north, ramregs[2*slot + 1], base);
|
||||
pci_write_config8(north, ramregs[2 * slot + 1], base);
|
||||
|
||||
if (!size)
|
||||
continue;
|
||||
|
|
@ -385,7 +386,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
print_debug(" is the chip size\r\n");
|
||||
if (size < 64)
|
||||
ma = 0;
|
||||
if (size < 256)
|
||||
else if (size < 256)
|
||||
ma = 8;
|
||||
else
|
||||
ma = 0xe;
|
||||
|
|
|
|||
|
|
@ -1,2 +1,8 @@
|
|||
config chip.h
|
||||
object vt8231.o
|
||||
driver vt8231.o
|
||||
driver vt8231_lpc.o
|
||||
driver vt8231_acpi.o
|
||||
driver vt8231_ide.o
|
||||
driver vt8231_nic.o
|
||||
#driver vt8231_usb.o
|
||||
|
||||
|
|
|
|||
|
|
@ -4,18 +4,10 @@
|
|||
extern struct chip_operations southbridge_via_vt8231_ops;
|
||||
|
||||
struct southbridge_via_vt8231_config {
|
||||
/* PCI function enables */
|
||||
/* i.e. so that pci scan bus will find them. */
|
||||
/* I am putting in IDE as an example but obviously this needs
|
||||
* to be more complete!
|
||||
*/
|
||||
int enable_ide;
|
||||
/* enables of functions of devices */
|
||||
int enable_usb;
|
||||
/* enables of Non-PCI devices */
|
||||
int enable_native_ide;
|
||||
int enable_com_ports;
|
||||
int enable_keyboard;
|
||||
int enable_nvram;
|
||||
};
|
||||
|
||||
#endif /* _SOUTHBRIDGE_VIA_VT8231 */
|
||||
|
|
|
|||
|
|
@ -1,281 +1,45 @@
|
|||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <console/console.h>
|
||||
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <pc80/keyboard.h>
|
||||
|
||||
#include "vt8231.h"
|
||||
#include "chip.h"
|
||||
|
||||
void pc_keyboard_init(void);
|
||||
/* Base 8231 controller */
|
||||
static device_t lpc_dev;
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
|
||||
}
|
||||
|
||||
static void usb_on(int enable)
|
||||
{
|
||||
unsigned char regval;
|
||||
|
||||
/* Base 8231 controller */
|
||||
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
|
||||
/* USB controller 1 */
|
||||
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
|
||||
/* USB controller 2 */
|
||||
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
|
||||
|
||||
/* enable USB1 */
|
||||
if(dev2) {
|
||||
if (enable) {
|
||||
pci_write_config8(dev2, 0x3c, 0x05);
|
||||
pci_write_config8(dev2, 0x04, 0x07);
|
||||
} else {
|
||||
pci_write_config8(dev2, 0x3c, 0x00);
|
||||
pci_write_config8(dev2, 0x04, 0x00);
|
||||
}
|
||||
}
|
||||
|
||||
if(dev0) {
|
||||
regval = pci_read_config8(dev0, 0x50);
|
||||
if (enable)
|
||||
regval &= ~(0x10);
|
||||
else
|
||||
regval |= 0x10;
|
||||
pci_write_config8(dev0, 0x50, regval);
|
||||
}
|
||||
|
||||
/* enable USB2 */
|
||||
if(dev3) {
|
||||
if (enable) {
|
||||
pci_write_config8(dev3, 0x3c, 0x05);
|
||||
pci_write_config8(dev3, 0x04, 0x07);
|
||||
} else {
|
||||
pci_write_config8(dev3, 0x3c, 0x00);
|
||||
pci_write_config8(dev3, 0x04, 0x00);
|
||||
}
|
||||
}
|
||||
|
||||
if(dev0) {
|
||||
regval = pci_read_config8(dev0, 0x50);
|
||||
if (enable)
|
||||
regval &= ~(0x20);
|
||||
else
|
||||
regval |= 0x20;
|
||||
pci_write_config8(dev0, 0x50, regval);
|
||||
}
|
||||
}
|
||||
|
||||
static void keyboard_on(void)
|
||||
{
|
||||
unsigned char regval;
|
||||
|
||||
/* Base 8231 controller */
|
||||
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
|
||||
|
||||
/* kevinh/Ispiri - update entire function to use
|
||||
new pci_write_config8 */
|
||||
|
||||
if (dev0) {
|
||||
regval = pci_read_config8(dev0, 0x51);
|
||||
if (lpc_dev) {
|
||||
regval = pci_read_config8(lpc_dev, 0x51);
|
||||
regval |= 0x0f;
|
||||
pci_write_config8(dev0, 0x51, regval);
|
||||
pci_write_config8(lpc_dev, 0x51, regval);
|
||||
}
|
||||
init_pc_keyboard(0x60, 0x64, 0);
|
||||
}
|
||||
|
||||
static void nvram_on(void)
|
||||
static void com_port_on(void)
|
||||
{
|
||||
/*
|
||||
* the VIA 8231 South has a very different nvram setup than the
|
||||
* piix4e ...
|
||||
* turn on ProMedia nvram.
|
||||
* TO DO: use the PciWriteByte function here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* kevinh/Ispiri - I don't think this is the correct address/value
|
||||
* intel_conf_writeb(0x80008841, 0xFF);
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Enable the ethernet device and turn off stepping (because it is integrated
|
||||
* inside the southbridge)
|
||||
*/
|
||||
static void ethernet_fixup()
|
||||
{
|
||||
device_t edev;
|
||||
uint8_t byte;
|
||||
|
||||
printk_info("Ethernet fixup\n");
|
||||
|
||||
edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
|
||||
if (edev) {
|
||||
printk_debug("Configuring VIA LAN\n");
|
||||
|
||||
/* We don't need stepping - though the device supports it */
|
||||
byte = pci_read_config8(edev, PCI_COMMAND);
|
||||
byte &= ~PCI_COMMAND_WAIT;
|
||||
pci_write_config8(edev, PCI_COMMAND, byte);
|
||||
} else {
|
||||
printk_debug("VIA LAN not found\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* we need to do things in this function so that PCI scan will find
|
||||
* them. One problem here is that we can't use ANY of the new device
|
||||
* stuff. This work here precedes all that.
|
||||
* Fundamental problem with linuxbios V2 architecture.
|
||||
* You can't do pci control in the C code without having done a PCI scan.
|
||||
* But in some cases you need to to pci control in the c code before doing
|
||||
* a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
|
||||
* that has functions with the same name but different type signatures
|
||||
* (e.g. device_t). This needs to get fixed. We need low-level pci scans
|
||||
* in the C code.
|
||||
*/
|
||||
static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf)
|
||||
{
|
||||
/*
|
||||
unsigned long busdevfn = 0x8000;
|
||||
if (conf->enable_ide) {
|
||||
printk_debug("%s: enabling IDE function\n", __FUNCTION__);
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
/* PIRQ init
|
||||
*/
|
||||
void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
|
||||
|
||||
|
||||
static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
|
||||
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
|
||||
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
|
||||
|
||||
/*
|
||||
Our IDSEL mappings are as follows
|
||||
PCI slot is AD31 (device 15) (00:14.0)
|
||||
Southbridge is AD28 (device 12) (00:11.0)
|
||||
*/
|
||||
static void pci_routing_fixup(struct device *dev)
|
||||
{
|
||||
|
||||
printk_info("%s: dev is %p\n", __FUNCTION__, dev);
|
||||
if (dev) {
|
||||
/* initialize PCI interupts - these assignments depend
|
||||
on the PCB routing of PINTA-D
|
||||
|
||||
PINTA = IRQ11
|
||||
PINTB = IRQ5
|
||||
PINTC = IRQ10
|
||||
PINTD = IRQ12
|
||||
*/
|
||||
pci_write_config8(dev, 0x55, 0xb0);
|
||||
pci_write_config8(dev, 0x56, 0xa5);
|
||||
pci_write_config8(dev, 0x57, 0xc0);
|
||||
}
|
||||
|
||||
// Standard southbridge components
|
||||
printk_info("setting southbridge\n");
|
||||
pci_assign_irqs(0, 0x11, southbridgeIrqs);
|
||||
|
||||
// Ethernet built into southbridge
|
||||
printk_info("setting ethernet\n");
|
||||
pci_assign_irqs(0, 0x12, enetIrqs);
|
||||
|
||||
// PCI slot
|
||||
printk_info("setting pci slot\n");
|
||||
pci_assign_irqs(0, 0x14, slotIrqs);
|
||||
printk_info("%s: DONE\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
dump_south(void)
|
||||
{
|
||||
device_t dev0;
|
||||
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
|
||||
int i,j;
|
||||
|
||||
for(i = 0; i < 256; i += 16) {
|
||||
printk_debug("0x%x: ", i);
|
||||
for(j = 0; j < 16; j++) {
|
||||
printk_debug("%02x ", pci_read_config8(dev0, i+j));
|
||||
}
|
||||
printk_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void vt8231_init(struct southbridge_via_vt8231_config *conf)
|
||||
{
|
||||
unsigned char enables;
|
||||
device_t dev0;
|
||||
device_t dev1;
|
||||
device_t devpwr;
|
||||
|
||||
// to do: use the pcibios_find function here, instead of
|
||||
// hard coding the devfn.
|
||||
// done - kevinh/Ispiri
|
||||
printk_debug("vt8231 init\n");
|
||||
/* Base 8231 controller */
|
||||
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
|
||||
/* IDE controller */
|
||||
dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
|
||||
/* Power management controller */
|
||||
devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
|
||||
|
||||
// enable the internal I/O decode
|
||||
enables = pci_read_config8(dev0, 0x6C);
|
||||
enables |= 0x80;
|
||||
pci_write_config8(dev0, 0x6C, enables);
|
||||
|
||||
// Map 4MB of FLASH into the address space
|
||||
pci_write_config8(dev0, 0x41, 0x7f);
|
||||
|
||||
// Set bit 6 of 0x40, because Award does it (IO recovery time)
|
||||
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
|
||||
// interrupts can be properly marked as level triggered.
|
||||
enables = pci_read_config8(dev0, 0x40);
|
||||
pci_write_config8(dev0, 0x40, enables);
|
||||
|
||||
// Set 0x42 to 0xf0 to match Award bios
|
||||
enables = pci_read_config8(dev0, 0x42);
|
||||
enables |= 0xf0;
|
||||
pci_write_config8(dev0, 0x42, enables);
|
||||
|
||||
// Set bit 3 of 0x4a, to match award (dummy pci request)
|
||||
enables = pci_read_config8(dev0, 0x4a);
|
||||
enables |= 0x08;
|
||||
pci_write_config8(dev0, 0x4a, enables);
|
||||
|
||||
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
|
||||
enables = pci_read_config8(dev0, 0x4f);
|
||||
enables |= 0x08;
|
||||
pci_write_config8(dev0, 0x4f, enables);
|
||||
|
||||
// Set 0x58 to 0x03 to match Award
|
||||
pci_write_config8(dev0, 0x58, 0x03);
|
||||
|
||||
// enable the ethernet/RTC
|
||||
if(dev0) {
|
||||
enables = pci_read_config8(dev0, 0x51);
|
||||
enables |= 0x18;
|
||||
pci_write_config8(dev0, 0x51, enables);
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
// enable com1 and com2.
|
||||
if (conf->enable_com_ports) {
|
||||
enables = pci_read_config8(dev0, 0x6e);
|
||||
enables = pci_read_config8(dev, 0x6e);
|
||||
|
||||
/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
|
||||
* is enable com port a as com1 kevinh/Ispiri - Old code
|
||||
* thought 0x01 would make it com1, that was wrong enables =
|
||||
* 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e,
|
||||
* 0x80 | 0x10 | 0x8 ; pci_write_config8(dev, 0x6e,
|
||||
* enables); // note: this is also a redo of some port of
|
||||
* assembly, but we want everything up.
|
||||
*/
|
||||
|
|
@ -283,159 +47,27 @@ static void vt8231_init(struct southbridge_via_vt8231_config *conf)
|
|||
/* set com1 to 115 kbaud not clear how to do this yet.
|
||||
* forget it; done in assembly.
|
||||
*/
|
||||
|
||||
}
|
||||
// enable IDE, since Linux won't do it.
|
||||
// First do some more things to devfn (17,0)
|
||||
// note: this should already be cleared, according to the book.
|
||||
enables = pci_read_config8(dev0, 0x50);
|
||||
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
|
||||
pci_write_config8(dev0, 0x50, enables);
|
||||
|
||||
// set default interrupt values (IDE)
|
||||
enables = pci_read_config8(dev0, 0x4c);
|
||||
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
|
||||
// clear out whatever was there.
|
||||
enables &= ~0xf;
|
||||
enables |= 4;
|
||||
printk_debug("setting reg. 4c to 0x%x\n", enables);
|
||||
pci_write_config8(dev0, 0x4c, enables);
|
||||
|
||||
// set up the serial port interrupts.
|
||||
// com2 to 3, com1 to 4
|
||||
pci_write_config8(dev0, 0x46, 0x04);
|
||||
pci_write_config8(dev0, 0x47, 0x03);
|
||||
pci_write_config8(dev0, 0x6e, 0x98);
|
||||
//
|
||||
// Power management setup
|
||||
//
|
||||
// Set ACPI base address to IO 0x4000
|
||||
pci_write_config32(devpwr, 0x48, 0x4001);
|
||||
|
||||
// Enable ACPI access (and setup like award)
|
||||
pci_write_config8(devpwr, 0x41, 0x84);
|
||||
|
||||
// Set hardware monitor base address to IO 0x6000
|
||||
pci_write_config32(devpwr, 0x70, 0x6001);
|
||||
|
||||
// Enable hardware monitor (and setup like award)
|
||||
pci_write_config8(devpwr, 0x74, 0x01);
|
||||
|
||||
// set IO base address to 0x5000
|
||||
pci_write_config32(devpwr, 0x90, 0x5001);
|
||||
|
||||
// Enable SMBus
|
||||
pci_write_config8(devpwr, 0xd2, 0x01);
|
||||
|
||||
//
|
||||
// IDE setup
|
||||
//
|
||||
if (! conf->enable_native_ide) {
|
||||
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
|
||||
// interrupts. Using PCI ints confuses linux for some reason.
|
||||
|
||||
printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
|
||||
enables = pci_read_config8(dev1, 0x42);
|
||||
printk_debug("enables in reg 0x42 0x%x\n", enables);
|
||||
enables &= ~0xc0; // compatability mode
|
||||
pci_write_config8(dev1, 0x42, enables);
|
||||
enables = pci_read_config8(dev1, 0x42);
|
||||
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
|
||||
}
|
||||
|
||||
enables = pci_read_config8(dev1, 0x40);
|
||||
printk_debug("enables in reg 0x40 0x%x\n", enables);
|
||||
enables |= 3;
|
||||
pci_write_config8(dev1, 0x40, enables);
|
||||
enables = pci_read_config8(dev1, 0x40);
|
||||
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
|
||||
|
||||
// Enable prefetch buffers
|
||||
enables = pci_read_config8(dev1, 0x41);
|
||||
enables |= 0xf0;
|
||||
pci_write_config8(dev1, 0x41, enables);
|
||||
|
||||
// Lower thresholds (cause award does it)
|
||||
enables = pci_read_config8(dev1, 0x43);
|
||||
enables &= ~0x0f;
|
||||
enables |= 0x05;
|
||||
pci_write_config8(dev1, 0x43, enables);
|
||||
|
||||
// PIO read prefetch counter (cause award does it)
|
||||
pci_write_config8(dev1, 0x44, 0x18);
|
||||
|
||||
// Use memory read multiple
|
||||
pci_write_config8(dev1, 0x45, 0x1c);
|
||||
|
||||
// address decoding.
|
||||
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
|
||||
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
|
||||
// used in native mode - I've changed back to classic
|
||||
enables = pci_read_config8(dev1, 0x9);
|
||||
printk_debug("enables in reg 0x9 0x%x\n", enables);
|
||||
// by the book, set the low-order nibble to 0xa.
|
||||
if (conf->enable_native_ide) {
|
||||
enables &= ~0xf;
|
||||
// cf/cg silicon needs an 'f' here.
|
||||
enables |= 0xf;
|
||||
} else {
|
||||
enables &= ~0x5;
|
||||
}
|
||||
|
||||
pci_write_config8(dev1, 0x9, enables);
|
||||
enables = pci_read_config8(dev1, 0x9);
|
||||
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
|
||||
|
||||
// standard bios sets master bit.
|
||||
enables = pci_read_config8(dev1, 0x4);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 7;
|
||||
|
||||
// No need for stepping - kevinh@ispiri.com
|
||||
enables &= ~0x80;
|
||||
|
||||
pci_write_config8(dev1, 0x4, enables);
|
||||
enables = pci_read_config8(dev1, 0x4);
|
||||
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
|
||||
|
||||
if (! conf->enable_native_ide) {
|
||||
// Use compatability mode - per award bios
|
||||
pci_write_config32(dev1, 0x10, 0x0);
|
||||
pci_write_config32(dev1, 0x14, 0x0);
|
||||
pci_write_config32(dev1, 0x18, 0x0);
|
||||
pci_write_config32(dev1, 0x1c, 0x0);
|
||||
|
||||
// Force interrupts to use compat mode - just like Award bios
|
||||
pci_write_config8(dev1, 0x3d, 00);
|
||||
pci_write_config8(dev1, 0x3c, 0xff);
|
||||
}
|
||||
|
||||
|
||||
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
|
||||
pci_write_config8(dev0, 0x40, 0x54);
|
||||
ethernet_fixup();
|
||||
|
||||
// Start the rtc
|
||||
rtc_init(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void southbridge_init(struct device *dev) {
|
||||
vt8231_init(dev->chip_info);
|
||||
pci_routing_fixup(dev);
|
||||
}
|
||||
|
||||
struct device_operations vt8231_dev_ops = {
|
||||
.init = &southbridge_init,
|
||||
};
|
||||
|
||||
static void southbridge_enable(struct device *dev)
|
||||
/* FixME: to be removed ? */
|
||||
static void vt8231_enable(struct device *dev)
|
||||
{
|
||||
dev->ops = &vt8231_dev_ops;
|
||||
struct southbridge_via_vt8231_config *conf = dev->chip_info;
|
||||
|
||||
if (!lpc_dev) {
|
||||
/* the first time called, enable devices not on PCI bus
|
||||
* FIXME: is that device struct there yet? */
|
||||
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
|
||||
PCI_DEVICE_ID_VIA_8231, 0);
|
||||
if (conf->enable_keyboard)
|
||||
keyboard_on();
|
||||
if (conf->enable_com_ports)
|
||||
com_port_on();
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations southbridge_via_vt8231_ops = {
|
||||
CHIP_NAME("VIA vt8231")
|
||||
.enable_dev = southbridge_enable,
|
||||
.enable_dev = vt8231_enable,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "vt8231.h"
|
||||
|
||||
static void acpi_init(struct device *dev)
|
||||
{
|
||||
printk_debug("Configuring VIA ACPI\n");
|
||||
|
||||
// Set ACPI base address to IO 0x4000
|
||||
pci_write_config32(dev, 0x48, 0x4001);
|
||||
|
||||
// Enable ACPI access (and setup like award)
|
||||
pci_write_config8(dev, 0x41, 0x84);
|
||||
|
||||
// Set hardware monitor base address to IO 0x6000
|
||||
pci_write_config32(dev, 0x70, 0x6001);
|
||||
|
||||
// Enable hardware monitor (and setup like award)
|
||||
pci_write_config8(dev, 0x74, 0x01);
|
||||
|
||||
// set IO base address to 0x5000
|
||||
pci_write_config32(dev, 0x90, 0x5001);
|
||||
|
||||
// Enable SMBus
|
||||
pci_write_config8(dev, 0xd2, 0x01);
|
||||
}
|
||||
|
||||
static struct device_operations acpi_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = acpi_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &acpi_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_8231_4,
|
||||
};
|
||||
|
|
@ -27,14 +27,13 @@ static void enable_smbus(void)
|
|||
device_t dev;
|
||||
unsigned char c;
|
||||
/* Power management controller */
|
||||
dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
|
||||
dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
|
||||
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("SMBUS controller not found\r\n");
|
||||
}
|
||||
|
||||
// set IO base address to SMBUS_IO_BASE
|
||||
pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
|
||||
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
|
||||
|
||||
// Enable SMBus
|
||||
c = pci_read_config8(dev, 0xd2);
|
||||
|
|
@ -43,7 +42,7 @@ static void enable_smbus(void)
|
|||
|
||||
/* make it work for I/O ...
|
||||
*/
|
||||
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
|
||||
dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
|
||||
c = pci_read_config8(dev, 4);
|
||||
c |= 1;
|
||||
pci_write_config8(dev, 4, c);
|
||||
|
|
@ -70,8 +69,8 @@ static int smbus_wait_until_active(void)
|
|||
if ((val & 1)) {
|
||||
break;
|
||||
}
|
||||
} while(--loops);
|
||||
return loops?0:-4;
|
||||
} while (--loops);
|
||||
return loops ? 0 : -4;
|
||||
}
|
||||
|
||||
static int smbus_wait_until_ready(void)
|
||||
|
|
@ -85,12 +84,11 @@ static int smbus_wait_until_ready(void)
|
|||
if ((val & 1) == 0) {
|
||||
break;
|
||||
}
|
||||
if(loops == (SMBUS_TIMEOUT / 2)) {
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
|
||||
SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
if (loops == (SMBUS_TIMEOUT / 2)) {
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
} while(--loops);
|
||||
return loops?0:-2;
|
||||
} while (--loops);
|
||||
return loops ? 0 : -2;
|
||||
}
|
||||
|
||||
static int smbus_wait_until_done(void)
|
||||
|
|
@ -102,11 +100,11 @@ static int smbus_wait_until_done(void)
|
|||
smbus_delay();
|
||||
|
||||
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
if ( (val & 1) == 0) {
|
||||
if ((val & 1) == 0) {
|
||||
break;
|
||||
}
|
||||
} while(--loops);
|
||||
return loops?0:-3;
|
||||
} while (--loops);
|
||||
return loops ? 0 : -3;
|
||||
}
|
||||
|
||||
void smbus_reset(void)
|
||||
|
|
@ -118,7 +116,7 @@ void smbus_reset(void)
|
|||
|
||||
smbus_wait_until_ready();
|
||||
print_debug("After reset status ");
|
||||
print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
|
||||
print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
|
|
@ -158,7 +156,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
|
|||
|
||||
if (smbus_wait_until_ready() < 0) {
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
if ( smbus_wait_until_ready() < 0 ) {
|
||||
if (smbus_wait_until_ready() < 0) {
|
||||
return -2;
|
||||
}
|
||||
}
|
||||
|
|
@ -171,12 +169,12 @@ static int smbus_read_byte(unsigned device, unsigned address)
|
|||
/* set the command/address... */
|
||||
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
|
||||
/* set up for a byte data read */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* clear any lingering errors, so the transaction will run */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* clear the data byte...*/
|
||||
/* clear the data byte... */
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
/* start a byte read, with interrupts disabled */
|
||||
|
|
@ -192,7 +190,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
|
|||
}
|
||||
|
||||
/* Ignore the Host Busy & Command Complete ? */
|
||||
global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1<<1)|(1<<0));
|
||||
global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0));
|
||||
|
||||
/* read results of transaction */
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
|
@ -206,8 +204,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
|
|||
#if 0
|
||||
/* SMBus routines borrowed from VIA's Trident Driver */
|
||||
/* this works, so I am not going to touch it for now -- rgm */
|
||||
static unsigned char smbus_read_byte(unsigned char devAdr,
|
||||
unsigned char bIndex)
|
||||
static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned char bData;
|
||||
|
|
@ -217,28 +214,28 @@ static unsigned char smbus_read_byte(unsigned char devAdr,
|
|||
outb(0xff, SMBUS_IO_BASE);
|
||||
|
||||
/* check SMBUS ready */
|
||||
for ( i = 0; i < SMBUS_TIMEOUT; i++ )
|
||||
if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
|
||||
for (i = 0; i < SMBUS_TIMEOUT; i++)
|
||||
if ((inb(SMBUS_IO_BASE) & 0x01) == 0)
|
||||
break;
|
||||
|
||||
/* set host command */
|
||||
outb(bIndex, SMBUS_IO_BASE+3);
|
||||
outb(bIndex, SMBUS_IO_BASE + 3);
|
||||
|
||||
/* set slave address */
|
||||
outb(devAdr | 0x01, SMBUS_IO_BASE+4);
|
||||
outb(devAdr | 0x01, SMBUS_IO_BASE + 4);
|
||||
|
||||
/* start */
|
||||
outb(0x48, SMBUS_IO_BASE+2);
|
||||
outb(0x48, SMBUS_IO_BASE + 2);
|
||||
|
||||
/* SMBUS Wait Ready */
|
||||
for ( i = 0; i < SMBUS_TIMEOUT; i++ )
|
||||
if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 )
|
||||
for (i = 0; i < SMBUS_TIMEOUT; i++)
|
||||
if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0)
|
||||
break;
|
||||
if ((sts & ~3) != 0) {
|
||||
smbus_print_error(sts);
|
||||
return 0;
|
||||
}
|
||||
bData=inb(SMBUS_IO_BASE+5);
|
||||
bData = inb(SMBUS_IO_BASE + 5);
|
||||
|
||||
return bData;
|
||||
|
||||
|
|
@ -265,18 +262,16 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
|
|||
/* set the command/address... */
|
||||
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
|
||||
/* set up for a byte data read */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
|
||||
SMBUS_IO_BASE + SMBHSTCTL);
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* clear any lingering errors, so the transaction will run */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* clear the data byte...*/
|
||||
/* clear the data byte... */
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
/* start the command */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
|
||||
SMBUS_IO_BASE + SMBHSTCTL);
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
smbus_wait_until_done();
|
||||
|
|
@ -296,4 +291,3 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
|
|||
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,108 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "vt8231.h"
|
||||
#include "chip.h"
|
||||
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_via_vt8231_config *conf;
|
||||
unsigned char enables;
|
||||
|
||||
if (!conf->enable_native_ide) {
|
||||
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
|
||||
// interrupts. Using PCI ints confuses linux for some reason.
|
||||
|
||||
printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
|
||||
enables = pci_read_config8(dev, 0x42);
|
||||
printk_debug("enables in reg 0x42 0x%x\n", enables);
|
||||
enables &= ~0xc0; // compatability mode
|
||||
pci_write_config8(dev, 0x42, enables);
|
||||
enables = pci_read_config8(dev, 0x42);
|
||||
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
|
||||
}
|
||||
|
||||
enables = pci_read_config8(dev, 0x40);
|
||||
printk_debug("enables in reg 0x40 0x%x\n", enables);
|
||||
enables |= 3;
|
||||
pci_write_config8(dev, 0x40, enables);
|
||||
enables = pci_read_config8(dev, 0x40);
|
||||
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
|
||||
|
||||
// Enable prefetch buffers
|
||||
enables = pci_read_config8(dev, 0x41);
|
||||
enables |= 0xf0;
|
||||
pci_write_config8(dev, 0x41, enables);
|
||||
|
||||
// Lower thresholds (cause award does it)
|
||||
enables = pci_read_config8(dev, 0x43);
|
||||
enables &= ~0x0f;
|
||||
enables |= 0x05;
|
||||
pci_write_config8(dev, 0x43, enables);
|
||||
|
||||
// PIO read prefetch counter (cause award does it)
|
||||
pci_write_config8(dev, 0x44, 0x18);
|
||||
|
||||
// Use memory read multiple
|
||||
pci_write_config8(dev, 0x45, 0x1c);
|
||||
|
||||
// address decoding.
|
||||
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
|
||||
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
|
||||
// used in native mode - I've changed back to classic
|
||||
enables = pci_read_config8(dev, 0x9);
|
||||
printk_debug("enables in reg 0x9 0x%x\n", enables);
|
||||
// by the book, set the low-order nibble to 0xa.
|
||||
if (conf->enable_native_ide) {
|
||||
enables &= ~0xf;
|
||||
// cf/cg silicon needs an 'f' here.
|
||||
enables |= 0xf;
|
||||
} else {
|
||||
enables &= ~0x5;
|
||||
}
|
||||
|
||||
pci_write_config8(dev, 0x9, enables);
|
||||
enables = pci_read_config8(dev, 0x9);
|
||||
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
|
||||
|
||||
// standard bios sets master bit.
|
||||
enables = pci_read_config8(dev, 0x4);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 7;
|
||||
|
||||
// No need for stepping - kevinh@ispiri.com
|
||||
enables &= ~0x80;
|
||||
|
||||
pci_write_config8(dev, 0x4, enables);
|
||||
enables = pci_read_config8(dev, 0x4);
|
||||
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
|
||||
|
||||
if (!conf->enable_native_ide) {
|
||||
// Use compatability mode - per award bios
|
||||
pci_write_config32(dev, 0x10, 0x0);
|
||||
pci_write_config32(dev, 0x14, 0x0);
|
||||
pci_write_config32(dev, 0x18, 0x0);
|
||||
pci_write_config32(dev, 0x1c, 0x0);
|
||||
|
||||
// Force interrupts to use compat mode - just like Award bios
|
||||
pci_write_config8(dev, 0x3d, 00);
|
||||
pci_write_config8(dev, 0x3c, 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_82C586_1,
|
||||
};
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
#include "vt8231.h"
|
||||
#include "chip.h"
|
||||
|
||||
/* PIRQ init
|
||||
*/
|
||||
void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
|
||||
static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
|
||||
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
|
||||
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
|
||||
|
||||
/*
|
||||
Our IDSEL mappings are as follows
|
||||
PCI slot is AD31 (device 15) (00:14.0)
|
||||
Southbridge is AD28 (device 12) (00:11.0)
|
||||
*/
|
||||
static void pci_routing_fixup(struct device *dev)
|
||||
{
|
||||
|
||||
printk_info("%s: dev is %p\n", __FUNCTION__, dev);
|
||||
if (dev) {
|
||||
/* initialize PCI interupts - these assignments depend
|
||||
on the PCB routing of PINTA-D
|
||||
|
||||
PINTA = IRQ11
|
||||
PINTB = IRQ5
|
||||
PINTC = IRQ10
|
||||
PINTD = IRQ12
|
||||
*/
|
||||
pci_write_config8(dev, 0x55, 0xb0);
|
||||
pci_write_config8(dev, 0x56, 0xa5);
|
||||
pci_write_config8(dev, 0x57, 0xc0);
|
||||
}
|
||||
|
||||
// Standard southbridge components
|
||||
printk_info("setting southbridge\n");
|
||||
pci_assign_irqs(0, 0x11, southbridgeIrqs);
|
||||
|
||||
// Ethernet built into southbridge
|
||||
printk_info("setting ethernet\n");
|
||||
pci_assign_irqs(0, 0x12, enetIrqs);
|
||||
|
||||
// PCI slot
|
||||
printk_info("setting pci slot\n");
|
||||
pci_assign_irqs(0, 0x14, slotIrqs);
|
||||
printk_info("%s: DONE\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void vt8231_init(struct device *dev)
|
||||
{
|
||||
unsigned char enables;
|
||||
struct southbridge_via_vt8231_config *conf = dev->chip_info;
|
||||
|
||||
printk_debug("vt8231 init\n");
|
||||
|
||||
// enable the internal I/O decode
|
||||
enables = pci_read_config8(dev, 0x6C);
|
||||
enables |= 0x80;
|
||||
pci_write_config8(dev, 0x6C, enables);
|
||||
|
||||
// Map 4MB of FLASH into the address space
|
||||
pci_write_config8(dev, 0x41, 0x7f);
|
||||
|
||||
// Set bit 6 of 0x40, because Award does it (IO recovery time)
|
||||
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
|
||||
// interrupts can be properly marked as level triggered.
|
||||
enables = pci_read_config8(dev, 0x40);
|
||||
pci_write_config8(dev, 0x40, enables);
|
||||
|
||||
// Set 0x42 to 0xf0 to match Award bios
|
||||
enables = pci_read_config8(dev, 0x42);
|
||||
enables |= 0xf0;
|
||||
pci_write_config8(dev, 0x42, enables);
|
||||
|
||||
// Set bit 3 of 0x4a, to match award (dummy pci request)
|
||||
enables = pci_read_config8(dev, 0x4a);
|
||||
enables |= 0x08;
|
||||
pci_write_config8(dev, 0x4a, enables);
|
||||
|
||||
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
|
||||
enables = pci_read_config8(dev, 0x4f);
|
||||
enables |= 0x08;
|
||||
pci_write_config8(dev, 0x4f, enables);
|
||||
|
||||
// Set 0x58 to 0x03 to match Award
|
||||
pci_write_config8(dev, 0x58, 0x03);
|
||||
|
||||
// enable the ethernet/RTC
|
||||
if (dev) {
|
||||
enables = pci_read_config8(dev, 0x51);
|
||||
enables |= 0x18;
|
||||
pci_write_config8(dev, 0x51, enables);
|
||||
}
|
||||
|
||||
// enable IDE, since Linux won't do it.
|
||||
// First do some more things to devfn (17,0)
|
||||
// note: this should already be cleared, according to the book.
|
||||
enables = pci_read_config8(dev, 0x50);
|
||||
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
|
||||
pci_write_config8(dev, 0x50, enables);
|
||||
|
||||
// set default interrupt values (IDE)
|
||||
enables = pci_read_config8(dev, 0x4c);
|
||||
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
|
||||
// clear out whatever was there.
|
||||
enables &= ~0xf;
|
||||
enables |= 4;
|
||||
printk_debug("setting reg. 4c to 0x%x\n", enables);
|
||||
pci_write_config8(dev, 0x4c, enables);
|
||||
|
||||
// set up the serial port interrupts.
|
||||
// com2 to 3, com1 to 4
|
||||
pci_write_config8(dev, 0x46, 0x04);
|
||||
pci_write_config8(dev, 0x47, 0x03);
|
||||
pci_write_config8(dev, 0x6e, 0x98);
|
||||
|
||||
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
|
||||
pci_write_config8(dev, 0x40, 0x54);
|
||||
//ethernet_fixup();
|
||||
|
||||
// Start the rtc
|
||||
rtc_init(0);
|
||||
}
|
||||
|
||||
static void southbridge_init(struct device *dev)
|
||||
{
|
||||
vt8231_init(dev);
|
||||
pci_routing_fixup(dev);
|
||||
}
|
||||
|
||||
static struct device_operations vt8231_lpc_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = &southbridge_init,
|
||||
.scan_bus = scan_static_bus,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &vt8231_lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_8231,
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "vt8231.h"
|
||||
|
||||
/*
|
||||
* Enable the ethernet device and turn off stepping (because it is integrated
|
||||
* inside the southbridge)
|
||||
*/
|
||||
static void nic_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
||||
printk_debug("Configuring VIA LAN\n");
|
||||
|
||||
/* We don't need stepping - though the device supports it */
|
||||
byte = pci_read_config8(dev, PCI_COMMAND);
|
||||
byte &= ~PCI_COMMAND_WAIT;
|
||||
pci_write_config8(dev, PCI_COMMAND, byte);
|
||||
}
|
||||
|
||||
static struct device_operations nic_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = nic_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &nic_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_8233_7,
|
||||
};
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
|
||||
static void usb_on(int enable)
|
||||
{
|
||||
unsigned char regval;
|
||||
|
||||
/* Base 8231 controller */
|
||||
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
|
||||
/* USB controller 1 */
|
||||
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
|
||||
/* USB controller 2 */
|
||||
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
|
||||
|
||||
/* enable USB1 */
|
||||
if(dev2) {
|
||||
if (enable) {
|
||||
pci_write_config8(dev2, 0x3c, 0x05);
|
||||
pci_write_config8(dev2, 0x04, 0x07);
|
||||
} else {
|
||||
pci_write_config8(dev2, 0x3c, 0x00);
|
||||
pci_write_config8(dev2, 0x04, 0x00);
|
||||
}
|
||||
}
|
||||
|
||||
if(dev0) {
|
||||
regval = pci_read_config8(dev0, 0x50);
|
||||
if (enable)
|
||||
regval &= ~(0x10);
|
||||
else
|
||||
regval |= 0x10;
|
||||
pci_write_config8(dev0, 0x50, regval);
|
||||
}
|
||||
|
||||
/* enable USB2 */
|
||||
if(dev3) {
|
||||
if (enable) {
|
||||
pci_write_config8(dev3, 0x3c, 0x05);
|
||||
pci_write_config8(dev3, 0x04, 0x07);
|
||||
} else {
|
||||
pci_write_config8(dev3, 0x3c, 0x00);
|
||||
pci_write_config8(dev3, 0x04, 0x00);
|
||||
}
|
||||
}
|
||||
|
||||
if(dev0) {
|
||||
regval = pci_read_config8(dev0, 0x50);
|
||||
if (enable)
|
||||
regval &= ~(0x20);
|
||||
else
|
||||
regval |= 0x20;
|
||||
pci_write_config8(dev0, 0x50, regval);
|
||||
}
|
||||
}
|
||||
|
|
@ -13,7 +13,8 @@ romimage "normal"
|
|||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
payload ../../../../../lnxieepro100.ebi
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
payload /etc/hosts
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
|
|
@ -22,7 +23,8 @@ romimage "fallback"
|
|||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
payload ../../../../../lnxieepro100.ebi
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
payload /etc/hosts
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
|
|
|
|||
Loading…
Reference in New Issue