lynxpoint xhci: Add ACPI D0/D3 workarounds
There are specific programming requirements for the usb3 ports on all LynxPoint chipsets when transitioning to D0 or D3. LynxPoint-LP has additional workaround steps needed involving resetting the disconnected ports when transitioning to D0. The workarounds are implemented in ACPI code so the controller can transition properly into D3 at runtime. Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62632 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4374 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
af98062817
commit
80fd5c4461
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@ -70,6 +70,296 @@ Device (XHCI)
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{
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{
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Name (_ADR, 0x00140000)
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Name (_ADR, 0x00140000)
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Name (PLSD, 5) // Port Link State - RxDetect
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Name (PLSP, 7) // Port Link State - Polling
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OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
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Field (XPRT, AnyAcc, NoLock, Preserve)
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{
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Offset (0x0),
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DVID, 16,
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Offset (0x10),
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, 16,
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XMEM, 16, // MEM_BASE
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Offset (0x74),
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D0D3, 2,
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, 6,
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PMEE, 1, // PME_EN
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, 6,
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PMES, 1, // PME_STS
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Offset (0xb0),
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, 13,
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MB13, 1,
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MB14, 1,
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Offset (0xd0),
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PR2R, 32, // USB2PR
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PR2M, 32, // USB2PRM
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PR3R, 32, // USB3PR
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PR3M, 32, // USB3PRM
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}
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// Clear status bits
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Method (LPCL, 0, Serialized)
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{
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OperationRegion (XREG, SystemMemory,
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ShiftLeft (^XMEM, 16), 0x600)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x510), // PORTSCNUSB3[0]
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, 17,
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CLR1, 7, // Status Change bits 23:17
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Offset (0x520), // PORTSCNUSB3[1]
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, 17,
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CLR2, 7, // Status Change Bits 23:17
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Offset (0x530), // PORTSCNUSB3[2]
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, 17,
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CLR3, 7, // Status Change Bits 23:17
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Offset (0x540), // PORTSCNUSB3[3]
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, 17,
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CLR4, 7, // Status Change Bits 23:17
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}
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Store (0x7f, CLR1)
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Store (0x7f, CLR2)
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Store (0x7f, CLR3)
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Store (0x7f, CLR4)
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}
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Method (LPS0, 0, Serialized)
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{
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OperationRegion (XREG, SystemMemory,
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ShiftLeft (^XMEM, 16), 0x600)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x510), // PORTSCNUSB3
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, 5,
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PLS1, 4, // [8:5] Port Link State
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PPR1, 1, // [9] Port Power
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, 7,
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CSC1, 1, // [17] Connect Status Change
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, 1,
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WRC1, 1, // [19] Warm Port Reset Change
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, 11,
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WPR1, 1, // [31] Warm Port Reset
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Offset (0x520), // PORTSCNUSB3
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, 5,
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PLS2, 4, // [8:5] Port Link State
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PPR2, 1, // [9] Port Power
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, 7,
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CSC2, 1, // [17] Connect Status Change
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, 1,
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WRC2, 1, // [19] Warm Port Reset Change
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, 11,
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WPR2, 1, // [31] Warm Port Reset
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Offset (0x530), // PORTSCNUSB3
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, 5,
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PLS3, 4, // [8:5] Port Link State
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PPR3, 1, // [9] Port Power
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, 7,
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CSC3, 1, // [17] Connect Status Change
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, 1,
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WRC3, 1, // [19] Warm Port Reset Change
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, 11,
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WPR3, 1, // [31] Warm Port Reset
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Offset (0x540), // PORTSCNUSB3
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, 5,
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PLS4, 4, // [8:5] Port Link State
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PPR4, 1, // [9] Port Power
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, 7,
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CSC4, 1, // [17] Connect Status Change
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, 1,
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WRC4, 1, // [19] Warm Port Reset Change
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, 11,
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WPR4, 1, // [31] Warm Port Reset
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}
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// Wait for all powered ports to finish polling
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Store (10, Local0)
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While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)),
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LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))),
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LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)),
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LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP)))))
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{
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If (LEqual (Local0, 0)) {
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Break
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}
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Decrement (Local0)
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Stall (10)
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}
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// For each USB3 Port:
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// If port is disconnected (PLS=5 PP=1 CSC=0)
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// 1) Issue warm reset (WPR=1)
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// 2) Poll for warm reset complete (WRC=0)
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// 3) Write 1 to port status to clear
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// Local# indicate if port is reset
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Store (0, Local1)
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Store (0, Local2)
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Store (0, Local3)
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Store (0, Local4)
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If (LAnd (LEqual (PLS1, PLSD),
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LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) {
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Store (1, WPR1) // Issue warm reset
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Store (1, Local1)
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}
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If (LAnd (LEqual (PLS2, PLSD),
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LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) {
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Store (1, WPR2) // Issue warm reset
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Store (1, Local2)
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}
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If (LAnd (LEqual (PLS3, PLSD),
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LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) {
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Store (1, WPR3) // Issue warm reset
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Store (1, Local3)
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}
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If (LAnd (LEqual (PLS4, PLSD),
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LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) {
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Store (1, WPR4) // Issue warm reset
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Store (1, Local4)
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}
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// Poll for warm reset complete on all ports that were reset
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Store (10, Local0)
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While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)),
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LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))),
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LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)),
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LAnd (LEqual (Local4, 1), LEqual (WRC4, 0)))))
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{
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If (LEqual (Local0, 0)) {
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Break
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}
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Decrement (Local0)
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Stall (10)
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}
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// Clear status bits in all ports
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LPCL ()
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}
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Method (_PS0, 0, Serialized)
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{
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If (LEqual (^DVID, 0xFFFF)) {
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Return ()
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}
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If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
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Return ()
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}
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OperationRegion (XREG, SystemMemory,
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Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x0e0), // AUX Reset Control 1
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, 15,
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AX15, 1,
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Offset (0x154), // AUX Domain PM Control Register 2
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, 31,
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CLK2, 1,
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Offset (0x16c), // AUX Clock Control
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, 2,
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CLK0, 1,
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, 11,
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CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
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}
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// If device is in D3, set back to D0
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Store (^D0D3, Local0)
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if (LEqual (Local0, 3)) {
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Store (0, ^D0D3)
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}
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If (\ISLP ()) {
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// Clear PCI 0xB0[14:13]
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Store (0, ^MB13)
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Store (0, ^MB14)
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// Clear MMIO 0x816C[14,2]
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Store (0, CLK0)
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Store (0, CLK1)
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}
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// Set MMIO 0x8154[31]
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Store (1, CLK2)
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If (\ISLP ()) {
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// Handle per-port reset if needed
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LPS0 ()
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// Set MMIO 0x80e0[15]
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Store (1, AX15)
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}
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// Put device in D3 if it was there originally
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If (LEqual (Local0, 3)) {
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Store (3, ^D0D3)
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}
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Return ()
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}
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Method (_PS3, 0, Serialized)
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{
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If (LEqual (^DVID, 0xFFFF)) {
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Return ()
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}
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If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
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Return ()
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}
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OperationRegion (XREG, SystemMemory,
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Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x0e0), // AUX Reset Control 1
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, 15,
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AX15, 1,
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Offset (0x154), // AUX Domain PM Control Register 2
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, 31,
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CLK2, 1,
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Offset (0x16c), // AUX Clock Control
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, 2,
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CLK0, 1,
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, 11,
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CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
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}
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Store (1, ^PMES) // Clear PME Status
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Store (1, ^PMEE) // Enable PME
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// If device is in D3, set back to D0
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Store (^D0D3, Local0)
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if (LEqual (Local0, 3)) {
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Store (0, ^D0D3)
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}
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If (\ISLP ()) {
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// Set PCI 0xB0[14:13]
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Store (1, ^MB13)
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Store (1, ^MB14)
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// Set MMIO 0x816C[14,2]
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Store (1, CLK0)
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Store (1, CLK1)
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}
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// Clear MMIO 0x8154[31]
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Store (0, CLK2)
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If (\ISLP ()) {
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// Clear MMIO 0x80e0[15]
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Store (0, AX15)
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}
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// Put device in D3
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If (LEqual (Local0, 3)) {
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Store (3, ^D0D3)
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}
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Return ()
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}
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Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
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Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
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Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
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Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
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