diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index e2fa0113ab..fd190ed714 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -136,32 +136,32 @@ static void issd_power_sequence(void)
 void mainboard_romstage_entry(unsigned long bist)
 {
 	struct pei_data pei_data = {
-		pei_version: PEI_VERSION,
-		mchbar: DEFAULT_MCHBAR,
-		dmibar: DEFAULT_DMIBAR,
-		epbar: DEFAULT_EPBAR,
-		pciexbar: DEFAULT_PCIEXBAR,
-		smbusbar: SMBUS_IO_BASE,
-		wdbbar: 0x4000000,
-		wdbsize: 0x1000,
-		hpet_address: HPET_ADDR,
-		rcba: DEFAULT_RCBA,
-		pmbase: DEFAULT_PMBASE,
-		gpiobase: DEFAULT_GPIOBASE,
-		temp_mmio_base: 0xfed08000,
-		system_type: 5, /* ULT */
-		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xff, 0x00, 0xff, 0x00 },
-		ec_present: 1,
+		.pei_version = PEI_VERSION,
+		.mchbar = DEFAULT_MCHBAR,
+		.dmibar = DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = DEFAULT_PCIEXBAR,
+		.smbusbar = SMBUS_IO_BASE,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = HPET_ADDR,
+		.rcba = DEFAULT_RCBA,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
+		.temp_mmio_base = 0xfed08000,
+		.system_type = 5, /* ULT */
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
+		.ec_present = 1,
 		// 0 = leave channel enabled
 		// 1 = disable dimm 0 on channel
 		// 2 = disable dimm 1 on channel
 		// 3 = disable dimm 0+1 on channel
-		dimm_channel0_disabled: 2,
-		dimm_channel1_disabled: 2,
-		max_ddr3_freq: 1600,
-		usb_xhci_on_resume: 1,
-		usb2_ports: {
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
+		.max_ddr3_freq = 1600,
+		.usb_xhci_on_resume = 1,
+		.usb2_ports = {
 			/* Length, Enable, OCn#, Location */
 			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
 			  USB_PORT_MINI_PCIE },
@@ -180,7 +180,7 @@ void mainboard_romstage_entry(unsigned long bist)
 			{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
 			  USB_PORT_SKIP },
 		},
-		usb3_ports: {
+		.usb3_ports = {
 			/* Enable, OCn# */
 			{ 1, 0               }, /* P1; Port A, CN10 */
 			{ 1, 2               }, /* P2; Port B, CN6  */