soc/intel/cannonlake: Add initial dummy directory
Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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config SOC_INTEL_CANNONLAKE
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bool
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help
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Intel Cannonlake support
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if SOC_INTEL_CANNONLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select HAVE_MONOTONIC_TIMER
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select REG_SCRIPT
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select C_ENVIRONMENT_BOOTBLOCK
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select HAVE_HARD_RESET
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select HAVE_INTEL_FIRMWARE
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select INTEL_CAR_NEM_ENHANCED
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select PLATFORM_USES_FSP2_0
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_SMBUS
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_CSE
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config UART_DEBUG
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bool "Enable UART debug port."
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default y
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select CONSOLE_SERIAL
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART
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select DRIVERS_UART_8250IO
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0x40000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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endif
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@ -0,0 +1,7 @@
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ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
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romstage-y += cbmem.c
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ramstage-y += cbmem.c
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endif
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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void *cbmem_top(void)
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{
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/* not implemented yet */
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return (void *) NULL;
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}
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