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mainboard/google/poppy: Use sideband IRQ for SD Card Detect 

Since SD card controller is expected to enter D3hot by runtime power
management if there is no card inserted, we need to use a sideband IRQ
pin which is not under the control of the controller. Thus, configure
GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect
pin.

BUG=b:35586693
BRANCH=None
TEST=Verified on a reworked poppy board that card detect works fine.

Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18926
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Furquan Shaikh 2017-03-20 10:53:57 -07:00 committed by Furquan Shaikh
parent bb5e77c478
commit 8110223989
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/poppy/devicetree.cb
View File

@ -177,7 +177,7 @@ chip soc/intel/skylake
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_G7"
register "sdcard_cd_gpio_default" = "GPP_A7"
device cpu_cluster 0 on
device lapic 0 on end

2
src/mainboard/google/poppy/gpio.h
View File

@ -48,7 +48,7 @@ static const struct pad_config gpio_table[] = {
/* ESPI_IO3 */
/* ESPI_CS# */
/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
/* PIRQA# */ PAD_CFG_NC(GPP_A7),
/* PIRQA# */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CD# */
/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
/* ESPI_CLK */
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),