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intel i945 gm45 x4x: Apply cbmem_top() alignment 

Force modest 4 MiB alignment to help with MTRR assignment.

Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17780
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-22 22:53:19 +03:00
parent 9d8adc0e3a
commit 811932a614
3 changed files with 19 additions and 4 deletions
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7
src/northbridge/intel/gm45/ram_calc.c
View File

@ -82,9 +82,14 @@ static uintptr_t smm_region_start(void)
return tor; return tor;
} }
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void) void *cbmem_top(void)
{ {
return (void *) smm_region_start(); uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
return (void *) top_of_ram;
} }
void *setup_stack_and_mtrrs(void) void *setup_stack_and_mtrrs(void)

7
src/northbridge/intel/i945/ram_calc.c
View File

@ -54,9 +54,14 @@ static uintptr_t smm_region_start(void)
return tom; return tom;
} }
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void) void *cbmem_top(void)
{ {
return (void *) smm_region_start(); uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
return (void *) top_of_ram;
} }
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ /** Decodes used Graphics Mode Select (GMS) to kilobytes. */

9
src/northbridge/intel/x4x/ram_calc.c
View File

@ -89,10 +89,15 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
return 1; return 1;
} }
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void) void *cbmem_top(void)
{ {
u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
return (void*)(ramtop); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB);
return (void *) top_of_ram;
} }
void *setup_stack_and_mtrrs(void) void *setup_stack_and_mtrrs(void)