From 813462ec31f4bc82488451e371c8d14d388d1e45 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 4 Oct 2017 15:05:17 -0600 Subject: [PATCH] amd/stoneyridge: Add function to find PmControl register Find the PmControl register's I/O address by checking the hardware in PMx62. Don't rely on the address being the coreboot default. PmControl is the first register in the AcpiPm1CntBlk. Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/21882 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Marc Jones --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 + src/soc/amd/stoneyridge/sb_util.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ebfee2499e..d506af979a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -202,6 +202,7 @@ u16 smi_read16(u8 reg); u32 smi_read32(u8 reg); void smi_write16(u8 reg, u16 value); void smi_write32(u8 reg, u32 value); +uint16_t pm_acpi_pm_cnt_blk(void); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 87bff70321..bdb199aa1e 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -64,3 +64,8 @@ void smi_write16(uint8_t offset, uint16_t value) { write16((void *)(APU_SMI_BASE + offset), value); } + +uint16_t pm_acpi_pm_cnt_blk(void) +{ + return pm_read16(PM1_CNT_BLK); +}