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nb/intel/sandybridge: Move constants out of for-loop 

Most per-channel registers are programmed with the same values.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: Ifddff3043b68113058859cef08625b90012ca424
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-11-12 13:46:21 +01:00 committed by Felix Held
parent 7a61274943
commit 8137806326
1 changed files with 60 additions and 54 deletions
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46
src/northbridge/intel/sandybridge/raminit_common.c
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@ -149,7 +149,6 @@ void dram_timing_regs(ramctr_timing *ctrl)
{
int channel;
FOR_ALL_CHANNELS {
/* BIN parameters */
const union tc_dbp_reg tc_dbp = {
.tRCD = ctrl->tRCD,
@ -158,8 +157,6 @@ void dram_timing_regs(ramctr_timing *ctrl)
.tCWL = ctrl->CWL,
.tRAS = ctrl->tRAS,
};
printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw);
MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw;
/* Regular access parameters */
const union tc_rap_reg tc_rap = {
@ -171,8 +168,6 @@ void dram_timing_regs(ramctr_timing *ctrl)
.tWR = ctrl->tWR,
.tCMD = 3,
};
printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw);
MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw;
/* Other parameters */
const union tc_othp_reg tc_othp = {
@ -182,11 +177,7 @@ void dram_timing_regs(ramctr_timing *ctrl)
.tCPDED = 2,
.tPRPDEN = 2,
};
printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw);
MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw;
/* Debug parameters - only applies to Ivy Bridge */
if (IS_IVY_CPU(ctrl->cpu)) {
/*
* If tXP and tXPDLL are very high, we need to increase them by one.
* This can only happen on Ivy Bridge, and when overclocking the RAM.
@ -195,10 +186,6 @@ void dram_timing_regs(ramctr_timing *ctrl)
.overclock_tXP = ctrl->tXP >= 8,
.overclock_tXPDLL = ctrl->tXPDLL >= 32,
};
MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw;
}
dram_odt_stretch(ctrl, channel);
/*
* TC-Refresh timing parameters:
@ -212,6 +199,32 @@ void dram_timing_regs(ramctr_timing *ctrl)
.tRFC = ctrl->tRFC,
.tREFIx9 = val32 / 1024,
};
/* Self-refresh timing parameters */
const union tc_srftp_reg tc_srftp = {
.tXSDLL = tDLLK,
.tXS_offset = ctrl->tXSOffset,
.tZQOPER = tDLLK - ctrl->tXSOffset,
.tMOD = ctrl->tMOD - 8,
};
FOR_ALL_CHANNELS {
printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw);
MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw;
printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw);
MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw;
printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw);
MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw;
if (IS_IVY_CPU(ctrl->cpu)) {
/* Debug parameters - only applies to Ivy Bridge */
MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw;
}
dram_odt_stretch(ctrl, channel);
printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw);
MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw;
@ -221,13 +234,6 @@ void dram_timing_regs(ramctr_timing *ctrl)
tc_rfp.oref_ri = 0xff;
MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw;
/* Self-refresh timing parameters */
const union tc_srftp_reg tc_srftp = {
.tXSDLL = tDLLK,
.tXS_offset = ctrl->tXSOffset,
.tZQOPER = tDLLK - ctrl->tXSOffset,
.tMOD = ctrl->tMOD - 8,
};
printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw);
MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw;
}