soc/intel/tigerlake: Enable SATA
Configure SATA FSP UPD according to mainboard design. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -121,6 +121,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* PCH UART selection for FSP Debug */
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params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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/* SATA */
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dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
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if (!dev)
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params->SataEnable = 0;
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else {
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params->SataEnable = dev->enabled;
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params->SataMode = config->SataMode;
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params->SataSalpSupport = config->SataSalpSupport;
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memcpy(params->SataPortsEnable, config->SataPortsEnable,
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sizeof(params->SataPortsEnable));
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memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
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sizeof(params->SataPortsDevSlp));
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}
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mainboard_silicon_init_params(params);
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}
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