From 8160a2f63db5a04a846b434701a88b449cc6f05f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 27 Jun 2016 13:24:11 +0300 Subject: [PATCH] intel post-car: Split legacy sockets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move old sockets to use romstage_legacy.c, these are ones using intel/car/cache_as_ram.inc. These will not be converted to RELOCATABLE_RAMSTAGE as boards are candidates for getting dropped from the tree anyways. Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/car/romstage_legacy.c | 20 ++++++++++++++++++++ src/cpu/intel/slot_1/Makefile.inc | 2 +- src/cpu/intel/socket_FC_PGA370/Makefile.inc | 2 +- src/cpu/intel/socket_PGA370/Makefile.inc | 2 +- src/cpu/intel/socket_mFCBGA479/Makefile.inc | 2 +- src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 +- 6 files changed, 25 insertions(+), 5 deletions(-) create mode 100644 src/cpu/intel/car/romstage_legacy.c diff --git a/src/cpu/intel/car/romstage_legacy.c b/src/cpu/intel/car/romstage_legacy.c new file mode 100644 index 0000000000..560cd7af2a --- /dev/null +++ b/src/cpu/intel/car/romstage_legacy.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void * asmlinkage romstage_main(unsigned long bist) +{ + mainboard_romstage_entry(bist); + return (void*)CONFIG_RAMTOP; +} diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 512571d318..ca7c154298 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -29,4 +29,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc -romstage-y += ../car/romstage.c +romstage-y += ../car/romstage_legacy.c diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc index cc6e299551..c06082c5ee 100644 --- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc @@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc -romstage-y += ../car/romstage.c +romstage-y += ../car/romstage_legacy.c diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc index d0f54051d6..9265ba458e 100644 --- a/src/cpu/intel/socket_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_PGA370/Makefile.inc @@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc -romstage-y += ../car/romstage.c +romstage-y += ../car/romstage_legacy.c diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc index c84659807a..918a54e800 100644 --- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc +++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc @@ -7,4 +7,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc -romstage-y += ../car/romstage.c +romstage-y += ../car/romstage_legacy.c diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc index 2a3187a8c0..c35ca462a0 100644 --- a/src/cpu/intel/socket_mPGA479M/Makefile.inc +++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc -romstage-y += ../car/romstage.c +romstage-y += ../car/romstage_legacy.c