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mb/emulation/qemu-q35: Consolidate host bridge definitions 

Move all Q35 register definitions into the q35.h header. Note that real
hardware does not have EXT_TSEG_MBYTES, because it is QEMU-specific.

Change-Id: I4c86ac0bb05563dee111b9b4a4a71c1c31198acd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50024
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-28 11:09:56 +01:00
parent 899525d92c
commit 816a41c904
6 changed files with 39 additions and 28 deletions
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3
src/mainboard/emulation/qemu-q35/acpi_tables.c
View File

@ -10,6 +10,7 @@
#include "../qemu-i440fx/fw_cfg.h"
#include "../qemu-i440fx/acpi.h"
#include "q35.h"
void mainboard_fill_fadt(acpi_fadt_t *fadt)
{
@ -46,7 +47,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
if (!dev)
return current;
reg = pci_read_config32(dev, 0x60);
reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
if ((reg & 0x07) != 0x01) /* require enabled + 256MB size */
return current;

6
src/mainboard/emulation/qemu-q35/bootblock.c
View File

@ -25,13 +25,13 @@ static void bootblock_northbridge_init(void)
* 4GiB.
*/
reg = 0;
pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg);
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */
pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg);
/* MCFG is now active. If it's not qemu was started for machine PC */
if (CONFIG(BOOTBLOCK_CONSOLE) &&
(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO) !=
(pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) !=
(CONFIG_MMCONF_BASE_ADDRESS | 1)))
die("You must run qemu for machine Q35 (-M q35)");
}

18
src/mainboard/emulation/qemu-q35/mainboard.c
View File

@ -5,7 +5,7 @@
#include <device/pci_ops.h>
#include <pc80/keyboard.h>
#define Q35_PAM0 0x90
#include "q35.h"
static const unsigned char qemu_q35_irqs[] = {
10, 10, 11, 11,
@ -16,15 +16,15 @@ static void qemu_nb_init(struct device *dev)
{
/* Map memory at 0xc0000 - 0xfffff */
int i;
uint8_t v = pci_read_config8(dev, Q35_PAM0);
uint8_t v = pci_read_config8(dev, D0F0_PAM(0));
v |= 0x30;
pci_write_config8(dev, Q35_PAM0, v);
pci_write_config8(dev, Q35_PAM0 + 1, 0x33);
pci_write_config8(dev, Q35_PAM0 + 2, 0x33);
pci_write_config8(dev, Q35_PAM0 + 3, 0x33);
pci_write_config8(dev, Q35_PAM0 + 4, 0x33);
pci_write_config8(dev, Q35_PAM0 + 5, 0x33);
pci_write_config8(dev, Q35_PAM0 + 6, 0x33);
pci_write_config8(dev, D0F0_PAM(0), v);
pci_write_config8(dev, D0F0_PAM(1), 0x33);
pci_write_config8(dev, D0F0_PAM(2), 0x33);
pci_write_config8(dev, D0F0_PAM(3), 0x33);
pci_write_config8(dev, D0F0_PAM(4), 0x33);
pci_write_config8(dev, D0F0_PAM(5), 0x33);
pci_write_config8(dev, D0F0_PAM(6), 0x33);
/* This sneaked in here, because Qemu does not emulate a SuperIO chip. */
pc_keyboard_init(NO_AUX_DEVICE);

17
src/mainboard/emulation/qemu-q35/memmap.c
View File

@ -8,21 +8,14 @@
#include <mainboard/emulation/qemu-i440fx/memory.h>
#include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
#define EXT_TSEG_MBYTES 0x50
#include "q35.h"
#define SMRAMC 0x9d
#define G_SMRAME (1 << 3)
#define D_LCK (1 << 4)
#define D_CLS (1 << 5)
#define D_OPEN (1 << 6)
#define ESMRAMC 0x9e
#define T_EN (1 << 0)
#define TSEG_SZ_MASK (3 << 1)
#define H_SMRAME (1 << 7)
/* QEMU-specific register */
#define EXT_TSEG_MBYTES 0x50
void smm_region(uintptr_t *start, size_t *size)
{
uint8_t esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
switch ((esmramc & TSEG_SZ_MASK) >> 1) {
case 0:
@ -35,7 +28,7 @@ void smm_region(uintptr_t *start, size_t *size)
*size = 8 * MiB;
break;
default:
*size = pci_read_config16(PCI_DEV(0, 0, 0), EXT_TSEG_MBYTES) * MiB;
*size = pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB;
}
*start = qemu_get_memory_size() * KiB - *size;

21
src/mainboard/emulation/qemu-q35/q35.h
View File

@ -3,7 +3,24 @@
#ifndef __MAINBOARD_EMU_Q35_H__
#define __MAINBOARD_EMU_Q35_H__
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
#include <device/pci_type.h>
#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */
#define SMRAMC 0x9d
#define G_SMRAME (1 << 3)
#define D_LCK (1 << 4)
#define D_CLS (1 << 5)
#define D_OPEN (1 << 6)
#define ESMRAMC 0x9e
#define T_EN (1 << 0)
#define TSEG_SZ_MASK (3 << 1)
#define H_SMRAME (1 << 7)
#endif

2
src/mainboard/emulation/qemu-q35/romstage.c
View File

@ -12,7 +12,7 @@ static void mainboard_machine_check(void)
{
/* Check that MCFG is active. If it's not qemu was started for machine PC */
if (!CONFIG(BOOTBLOCK_CONSOLE) &&
(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO) !=
(pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) !=
(CONFIG_MMCONF_BASE_ADDRESS | 1)))
die("You must run qemu for machine Q35 (-M q35)");
}