GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

pci1x2x: remove latency/bridge control/cacheline size settings 

Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Sven Schnelle 2011-04-20 08:58:38 +00:00
parent 5c72a8752b
commit 81725b2eff
3 changed files with 0 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/nokia/ip530/devicetree.cb
View File

@ -33,8 +33,6 @@ chip northbridge/intel/i440bx # Northbridge
device pci 00.0 on
subsystemid 0x13b8 0x0000
end
register "cltr" = "0x40"
register "bcr" = "0x7c0"
register "scr" = "0x08449060"
register "mrr" = "0x00007522"
end

3
src/southbridge/ti/pci1x2x/chip.h
View File

@ -6,8 +6,5 @@ extern struct chip_operations southbridge_ti_pci1x2x_ops;
struct southbridge_ti_pci1x2x_config {
int scr;
int mrr;
int clsr;
int cltr;
int bcr;
};
#endif

6
src/southbridge/ti/pci1x2x/pci1x2x.c
View File

@ -34,12 +34,6 @@ static void ti_pci1x2y_init(struct device *dev)
struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
if (conf) {
/* Cache Line Size (offset 0x0C) */
pci_write_config8(dev, 0x0C, conf->clsr);
/* CardBus latency timer (offset 0x1B) */
pci_write_config8(dev, 0x1B, conf->cltr);
/* Bridge control (offset 0x3E) */
pci_write_config16(dev, 0x3E, conf->bcr);
/* System control (offset 0x80) */
pci_write_config32(dev, 0x80, conf->scr);
/* Multifunction routing */