mb/purism/librem_bdw: Convert to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier
Patrick Georgi
parent
eba32d217a
commit
819005332b
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@ -17,9 +17,9 @@ config VARIANT_DIR
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default "librem13v1" if BOARD_PURISM_LIBREM13_V1
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default "librem15v2" if BOARD_PURISM_LIBREM15_V2
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config DEVICETREE
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config DRIVERS_UART_8250IO
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def_bool n
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@ -21,14 +21,6 @@ chip soc/intel/broadwell
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register "gen1_dec" = "0x00000381"
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register "gen2_dec" = "0x000c0081"
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# Port 0 is HDD
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# Port 1 is M.2 NGFF
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register "sata_port_map" = "0x3"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "7"
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register "sata_port1_gen3_dtle" = "9"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -58,7 +50,7 @@ chip soc/intel/broadwell
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device pci 1c.3 on end # PCIe Port #4 - WiFi
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
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device pci 1d.0 on end # USB2 EHCI
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device pci 1d.0 off end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip ec/purism/librem
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@ -1,72 +0,0 @@
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chip soc/intel/broadwell
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable DDI1 Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Set backlight PWM value for eDP
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register "gpu_pch_backlight_pwm_hz" = "200"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "6" # 500ms
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register "gpu_panel_power_up_delay" = "2000" # 200ms
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register "gpu_panel_power_down_delay" = "500" # 50ms
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register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
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# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
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register "gen1_dec" = "0x00000381"
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register "gen2_dec" = "0x000c0081"
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# Port 0 is HDD
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# Port 3 is M.2 NGFF
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register "sata_port_map" = "0x9"
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# Port 0 tuning for link stability
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register "sata_port0_gen3_dtle" = "9"
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register "sata_port3_gen3_dtle" = "9"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 off end # Serial I/O DMA
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device pci 15.1 off end # I2C0
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device pci 15.2 off end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 on end # PCIe Port #3 - LAN
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device pci 1c.3 on end # PCIe Port #4 - WiFi
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
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device pci 1d.0 off end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip ec/purism/librem
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device pnp 0c09.0 on end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 off end # Thermal
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end
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end
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@ -0,0 +1,14 @@
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chip soc/intel/broadwell
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# Port 0 is HDD
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# Port 3 is M.2 NGFF
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register "sata_port_map" = "0x9"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "9"
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register "sata_port3_gen3_dtle" = "9"
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device domain 0 on
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device pci 1c.2 on end # PCIe Port #3 - LAN
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end
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end
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@ -0,0 +1,14 @@
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chip soc/intel/broadwell
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# Port 0 is HDD
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# Port 1 is M.2 NGFF
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register "sata_port_map" = "0x3"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "7"
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register "sata_port1_gen3_dtle" = "9"
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device domain 0 on
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device pci 1d.0 on end # USB2 EHCI
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end
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end
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