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mb/purism/librem_bdw: Convert to use override devicetree 

Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier 2020-04-30 16:12:05 -05:00 committed by Patrick Georgi
parent eba32d217a
commit 819005332b
5 changed files with 31 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/purism/librem_bdw/Kconfig
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@ -17,9 +17,9 @@ config VARIANT_DIR
default "librem13v1" if BOARD_PURISM_LIBREM13_V1 default "librem13v1" if BOARD_PURISM_LIBREM13_V1
default "librem15v2" if BOARD_PURISM_LIBREM15_V2 default "librem15v2" if BOARD_PURISM_LIBREM15_V2
config DEVICETREE config OVERRIDE_DEVICETREE
string string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config DRIVERS_UART_8250IO config DRIVERS_UART_8250IO
def_bool n def_bool n

10
src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb → src/mainboard/purism/librem_bdw/devicetree.cb
View File

@ -21,14 +21,6 @@ chip soc/intel/broadwell
register "gen1_dec" = "0x00000381" register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081" register "gen2_dec" = "0x000c0081"
# Port 0 is HDD
# Port 1 is M.2 NGFF
register "sata_port_map" = "0x3"
# Port tuning for link stability
register "sata_port0_gen3_dtle" = "7"
register "sata_port1_gen3_dtle" = "9"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end
@ -58,7 +50,7 @@ chip soc/intel/broadwell
device pci 1c.3 on end # PCIe Port #4 - WiFi device pci 1c.3 on end # PCIe Port #4 - WiFi
device pci 1c.4 on end # PCIe Port #5 device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
device pci 1d.0 on end # USB2 EHCI device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge device pci 1e.0 off end # PCI bridge
device pci 1f.0 on device pci 1f.0 on
chip ec/purism/librem chip ec/purism/librem

72
src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb
View File

@ -1,72 +0,0 @@
chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081"
# Port 0 is HDD
# Port 3 is M.2 NGFF
register "sata_port_map" = "0x9"
# Port 0 tuning for link stability
register "sata_port0_gen3_dtle" = "9"
register "sata_port3_gen3_dtle" = "9"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3 - LAN
device pci 1c.3 on end # PCIe Port #4 - WiFi
device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip ec/purism/librem
device pnp 0c09.0 on end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
end
end

14
src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb Normal file
View File

@ -0,0 +1,14 @@
chip soc/intel/broadwell
# Port 0 is HDD
# Port 3 is M.2 NGFF
register "sata_port_map" = "0x9"
# Port tuning for link stability
register "sata_port0_gen3_dtle" = "9"
register "sata_port3_gen3_dtle" = "9"
device domain 0 on
device pci 1c.2 on end # PCIe Port #3 - LAN
end
end

14
src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb Normal file
View File

@ -0,0 +1,14 @@
chip soc/intel/broadwell
# Port 0 is HDD
# Port 1 is M.2 NGFF
register "sata_port_map" = "0x3"
# Port tuning for link stability
register "sata_port0_gen3_dtle" = "7"
register "sata_port1_gen3_dtle" = "9"
device domain 0 on
device pci 1d.0 on end # USB2 EHCI
end
end