asus/p2b: Align ACPI tables with asus/p2b-ls
Updates ACPI tables with work done for asus/p2b-ls, including super I/O related declarations. Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Keith Hui
Stefan Reinauer
parent
cd2c3334c4
commit
819005f58b
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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* Copyright (C) 2017 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -15,8 +16,29 @@
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#include "southbridge/intel/i82371eb/i82371eb.h"
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#define SUPERIO_PNP_BASE 0x3F0
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#define SUPERIO_SHOW_UARTA
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#define SUPERIO_SHOW_UARTB
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#define SUPERIO_SHOW_FDC
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#define SUPERIO_SHOW_LPT
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DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
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{
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/* \_PR scope defining the main processor is generated in SSDT. */
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OperationRegion(X80, SystemIO, 0x80, 1)
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Field(X80, ByteAcc, NoLock, Preserve)
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{
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P80, 8
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}
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/*
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* For now only define 2 power states:
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* - S0 which is fully on
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* - S5 which is soft off
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* Any others would involve declaring the wake up methods.
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*/
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/*
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* Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
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*
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@ -38,25 +60,41 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
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Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })
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Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
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OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)
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Field (SIO1, ByteAcc, NoLock, Preserve)
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OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10)
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Field (GPOB, ByteAcc, NoLock, Preserve)
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{
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FANP, 1, /* CPU/case fan power */
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Offset (0x01),
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PLED, 1,
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Offset (0x03),
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TO12, 1, /* Device trap 12 */
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Offset (0x08),
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FANM, 1, /* GPO0, meant for fan */
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Offset (0x09),
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PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */
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, 3, /* this goes low when power is cut from its core. */
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, 2,
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, 16,
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MSG0, 1 /* GPO30, message LED */
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}
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/* Prepare To Sleep, Arg0 is target S-state */
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Method (\_PTS, 1, NotSerialized)
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{
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/* Disable fan, blink power led */
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Store (Zero, FANP)
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/* Disable fan, blink power LED, if not turning off */
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If (LNotEqual (Arg0, 0x05))
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{
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Store (Zero, FANM)
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Store (Zero, PLED)
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}
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/* Arms SMI for device 12 */
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Store (One, TO12)
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/* Put out a POST code */
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Or (Arg0, 0xF0, P80)
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}
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Method (\_WAK, 1, NotSerialized)
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{
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/* Re-enable fan, stop power led blinking */
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Store (One, FANP)
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Store (One, FANM)
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Store (One, PLED)
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/* wake OK */
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Return(Package(0x02){0x00, 0x00})
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@ -65,6 +103,22 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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Device (PWRB)
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{
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/* Power Button Device */
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Name (_HID, EisaId ("PNP0C0C"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0B)
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}
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}
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#include "southbridge/intel/i82371eb/acpi/intx.asl"
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PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)
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PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)
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PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3)
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PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4)
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/* Top PCI device */
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Device (PCI0)
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{
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@ -106,10 +160,97 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
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Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
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})
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#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"
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#include "southbridge/intel/i82371eb/acpi/isabridge.asl"
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/* Begin southbridge block */
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Device (PX40)
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{
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Name(_ADR, 0x00040000)
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OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
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Field (PIRQ, ByteAcc, NoLock, Preserve)
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{
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PIRA, 8,
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PIRB, 8,
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PIRC, 8,
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PIRD, 8
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}
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/* PNP Motherboard Resources */
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Device (SYSR)
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{
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Name (_HID, EisaId ("PNP0C02"))
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF1, ResourceTemplate ()
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{
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/* PM register ports */
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IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
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/* SMBus register ports */
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IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
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/* PIIX4E ports */
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/* Aliased DMA ports */
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IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
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/* Aliased PIC ports */
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IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )
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/* Aliased timer ports */
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IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, )
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IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )
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IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )
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IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )
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IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )
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IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )
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IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )
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IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )
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IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
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IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
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})
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CreateWordField (BUF1, _Y06._MIN, PMLO)
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CreateWordField (BUF1, _Y06._MAX, PMRL)
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CreateWordField (BUF1, _Y07._MIN, SBLO)
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CreateWordField (BUF1, _Y07._MAX, SBRL)
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And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO)
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And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO)
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Store (PMLO, PMRL)
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Store (SBLO, SBRL)
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Return (BUF1)
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}
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}
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#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"
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}
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Device (PX43)
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{
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Name (_ADR, 0x00040003) // _ADR: Address
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OperationRegion (IPMU, PCI_Config, PMBA, 0x02)
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Field (IPMU, ByteAcc, NoLock, Preserve)
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{
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PM00, 16
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}
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OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)
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Field (ISMB, ByteAcc, NoLock, Preserve)
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{
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SB00, 16
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}
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}
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#include "superio/winbond/w83977tf/acpi/superio.asl"
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}
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}
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/* ACPI Message */
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Scope (\_SI)
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{
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Method (_MSG, 1, NotSerialized)
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{
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If (LEqual (Arg0, Zero))
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{
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Store (One, MSG0)
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}
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Else
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{
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Store (Zero, MSG0)
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}
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}
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#include "southbridge/intel/i82371eb/acpi/pirq.asl"
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}
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}
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