Add support for SMSC LPC47N207 SuperI/O chip
This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/823 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* This code tries to discover the SMSC LPC47N207 superio chip which can be
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* connected over an LPC dongle. The chip could be bootstrap mapped to one of
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* four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e.
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*
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* Initializing the UART requires accesses to a few control registers. This
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* structure includes the register offset and the value to write (along with
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* the mask).
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*/
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typedef struct {
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u8 conf_reg;
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u8 value;
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u8 mask;
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} uart_conf;
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/* All regs/values to write to initialize the LPC47N207 UART */
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static const uart_conf uart_conf_data [] = {
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{2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */
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{0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */
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{0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */
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};
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void try_enabling_LPC47N207_uart(void)
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{
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u8 reg_value;
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const uart_conf* conf_item;
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u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
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u16 lpc_port;
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int i, j;
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#define CONFIG_ENABLE 0x55
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#define CONFIG_DISABLE 0xaa
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for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) {
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lpc_port = lpc_ports[j];
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/* enable CONFIG mode */
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outb(CONFIG_ENABLE, lpc_port);
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reg_value=inb(lpc_port);
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if (reg_value != CONFIG_ENABLE) {
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continue; /* There is no LPC device at this address */
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}
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do {
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/*
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* Registers 12 and 13 hold config address, look for a
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* match.
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*/
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outb(0x12, lpc_port);
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reg_value=inb(lpc_port + 1);
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if (reg_value != (lpc_port & 0xff))
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break;
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outb(0x13, lpc_port);
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reg_value=inb(lpc_port + 1);
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if (reg_value != (lpc_port >> 8))
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break;
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/* This must be the SMSC LPC 47N207, enable the UART. */
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for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) {
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u8 reg, value, mask;
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conf_item = uart_conf_data + i;
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reg = conf_item->conf_reg;
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value = conf_item->value;
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mask = conf_item->mask;
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outb(reg, lpc_port);
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reg_value = inb(lpc_port + 1);
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reg_value &= ~mask;
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reg_value |= (value & mask);
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outb(reg_value, lpc_port + 1);
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}
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} while (0);
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outb(CONFIG_DISABLE, lpc_port);
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}
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}
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H
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#define SUPERIO_SMSC_LPC47N207_LPC47N207_H
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extern void try_enabling_LPC47N207_uart(void);
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#endif
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