soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers

This patch save and restore ITSS IPCx register before and after
FSP-S call.

Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/chip.c

@@ -21,9 +21,11 @@
 #include <fsp/util.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/chip.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
+#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>
@@ -96,11 +98,18 @@ const char *soc_acpi_name(const struct device *dev)
 
 void soc_init_pre_device(void *chip_info)
 {
+	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
+	 * default policy that doesn't honor boards' requirements. */
+	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
 	/* Perform silicon specific init. */
 	fsp_silicon_init(romstage_handoff_is_resume());
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
+
+	/* Restore GPIO IRQ polarities back to previous settings. */
+	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 }
 
 static void pci_domain_set_resources(struct device *dev)

src/soc/intel/cannonlake/include/soc/itss.h

@@ -16,6 +16,9 @@
 #ifndef SOC_INTEL_CNL_ITSS_H
 #define SOC_INTEL_CNL_ITSS_H
 
+#define GPIO_IRQ_START	50
+#define GPIO_IRQ_END	ITSS_MAX_IRQ
+
 #define ITSS_MAX_IRQ	119
 #define IRQS_PER_IPC	32
 #define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)