soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers

This patch save and restore ITSS IPCx register before and after
FSP-S call.

Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-09-28 19:56:54 +05:30 committed by Duncan Laurie
parent 46caf09598
commit 819b143925
2 changed files with 12 additions and 0 deletions

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@ -21,9 +21,11 @@
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/acpi.h> #include <intelblocks/acpi.h>
#include <intelblocks/chip.h> #include <intelblocks/chip.h>
#include <intelblocks/itss.h>
#include <intelblocks/xdci.h> #include <intelblocks/xdci.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <soc/intel/common/vbt.h> #include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <string.h> #include <string.h>
@ -96,11 +98,18 @@ const char *soc_acpi_name(const struct device *dev)
void soc_init_pre_device(void *chip_info) void soc_init_pre_device(void *chip_info)
{ {
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */ /* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume()); fsp_silicon_init(romstage_handoff_is_resume());
/* Display FIRMWARE_VERSION_INFO_HOB */ /* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob(); fsp_display_fvi_version_hob();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
} }
static void pci_domain_set_resources(struct device *dev) static void pci_domain_set_resources(struct device *dev)

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@ -16,6 +16,9 @@
#ifndef SOC_INTEL_CNL_ITSS_H #ifndef SOC_INTEL_CNL_ITSS_H
#define SOC_INTEL_CNL_ITSS_H #define SOC_INTEL_CNL_ITSS_H
#define GPIO_IRQ_START 50
#define GPIO_IRQ_END ITSS_MAX_IRQ
#define ITSS_MAX_IRQ 119 #define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32 #define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)