soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -21,9 +21,11 @@
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#include <fsp/util.h>
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#include <intelblocks/acpi.h>
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#include <intelblocks/chip.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/xdci.h>
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#include <romstage_handoff.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/itss.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <string.h>
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@ -96,11 +98,18 @@ const char *soc_acpi_name(const struct device *dev)
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void soc_init_pre_device(void *chip_info)
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{
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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* default policy that doesn't honor boards' requirements. */
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itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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/* Perform silicon specific init. */
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fsp_silicon_init(romstage_handoff_is_resume());
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/* Display FIRMWARE_VERSION_INFO_HOB */
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fsp_display_fvi_version_hob();
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/* Restore GPIO IRQ polarities back to previous settings. */
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itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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}
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static void pci_domain_set_resources(struct device *dev)
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@ -16,6 +16,9 @@
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#ifndef SOC_INTEL_CNL_ITSS_H
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#define SOC_INTEL_CNL_ITSS_H
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#define GPIO_IRQ_START 50
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#define GPIO_IRQ_END ITSS_MAX_IRQ
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#define ITSS_MAX_IRQ 119
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#define IRQS_PER_IPC 32
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#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
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