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mb/google/dedede: Fix S3 wake using trackpad 

Configure TRACKPAD_INT_ODL pad reset config to DEEP and
map PMC_GPE_DW to PMC_GPP values.

TEST=System should wake from S3 via trackpad

Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Meera Ravindranath 2020-07-27 12:05:26 +05:30 committed by Subrata Banik
parent d980339aca
commit 819d676fed
2 changed files with 4 additions and 4 deletions
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6
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@ -16,9 +16,9 @@ chip soc/intel/jasperlake
# - GPP_D0 - WWAN_HOST_WAKE # - GPP_D0 - WWAN_HOST_WAKE
# - GPP_D3 - WLAN_PCIE_WAKE_ODL # - GPP_D3 - WLAN_PCIE_WAKE_ODL
# EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
register "pmc_gpe0_dw0" = "GPP_B" register "pmc_gpe0_dw0" = "PMC_GPP_B"
register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw1" = "PMC_GPP_C"
register "pmc_gpe0_dw2" = "GPP_D" register "pmc_gpe0_dw2" = "PMC_GPP_D"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801" register "gen1_dec" = "0x00fc0801"

2
src/mainboard/google/dedede/variants/baseboard/gpio.c
View File

@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = {
/* B2 : PROCHOT_ODL */ /* B2 : PROCHOT_ODL */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
/* B3 : TRACKPAD_INT_ODL */ /* B3 : TRACKPAD_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, LEVEL, INVERT),
/* B4 : H1_PCH_INT_ODL */ /* B4 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
/* B5 : PCIE_CLKREQ0_N */ /* B5 : PCIE_CLKREQ0_N */