mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up. Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Thomas Heijligen
Patrick Georgi
parent
1d9b059c52
commit
819d872606
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_SIEMENS_CHILI_BASE
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE
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select EC_ACPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_USES_IFD_GBE_REGION
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select SOC_INTEL_CANNONLAKE_PCH_H
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select SOC_INTEL_COFFEELAKE
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config MAINBOARD_DIR
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string
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default "siemens/chili"
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config MAINBOARD_FAMILY
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string
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default "Chili"
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config MAINBOARD_PART_NUMBER
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string
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default "Chili base board"
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config VARIANT_DIR
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string
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default "base" if BOARD_SIEMENS_CHILI_BASE
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config INTEL_GMA_VBT_FILE
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string
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default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
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config DIMM_SPD_SIZE
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int
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default 512
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config CBFS_SIZE
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hex
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default 0xb00000
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config POST_DEVICE
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bool
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default n
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endif
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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comment "CHILI"
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config BOARD_SIEMENS_CHILI_BASE
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bool "-> Base board"
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## SPDX-License-Identifier: GPL-2.0-only
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
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romstage-y += romstage.c
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ramstage-y += mainboard.c
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ramstage-y += ec.c
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smm-y += ec.c
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subdirs-y += variants/$(VARIANT_DIR)
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Vendor name: Siemens
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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0 120 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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401 1 e 2 vtd
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# coreboot config options: pch
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408 2 e 4 power_on_after_fail
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# coreboot config options: mainboard
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440 1 e 2 ethernet1
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# payload config options
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512 256 s 0 boot_devices
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768 8 h 0 boot_default
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784 1 e 1 cmos_defaults_loaded
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 No
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1 1 Yes
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2 0 Disable
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2 1 Enable
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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4 0 Disable
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4 1 Enable
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4 2 Keep
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <ec/acpi/ec.h>
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#include <timer.h>
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#include "ec.h"
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#define EC_STATUS 0x50
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#define EC_RUNNING (1 << 1)
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#define EC_DEVICE_CONTROL_1 0x80
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#define EC_DEVICE_CONTROL_1_PROGAS_ON (1 << 0)
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#define EC_DEVICE_CONTROL_1_BOOMER_ON (1 << 1)
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#define EC_DEVICE_CONTROL_1_BT_RF_ON (1 << 2)
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#define EC_DEVICE_CONTROL_1_TP_ON (1 << 3)
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#define EC_DEVICE_CONTROL_1_LAN2_RST (1 << 6)
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#define EC_DEVICE_CONTROL_2 0x81
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#define EC_DEVICE_CONTROL_2_LAN_1_ON (1 << 0)
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#define EC_DEVICE_CONTROL_2_LAN_2_ON (1 << 1)
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#define EC_DEVICE_CONTROL_2_WLAN_ON (1 << 2)
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#define EC_DEVICE_CONTROL_2_USB_ON (1 << 3)
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#define EC_DEVICE_CONTROL_2_IDE1_ON (1 << 4)
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#define EC_DEVICE_CONTROL_2_IDE2_ON (1 << 5)
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#define EC_DEVICE_CONTROL_2_COM1_ON (1 << 6)
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#define EC_DEVICE_CONTROL_2_MPI_ON (1 << 7)
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#define RUNNING_TIMEOUT_MS 3333
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static bool ec_running(void)
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{
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struct stopwatch sw;
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uint8_t ec_status;
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stopwatch_init_msecs_expire(&sw, RUNNING_TIMEOUT_MS);
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do
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ec_status = ec_read(EC_STATUS);
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while (!(ec_status & EC_RUNNING) && !stopwatch_expired(&sw));
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if (!(ec_status & EC_RUNNING))
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printk(BIOS_WARNING, "EC not ready after %dms\n", RUNNING_TIMEOUT_MS);
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return !!(ec_status & EC_RUNNING);
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}
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void ec_enable_devices(bool enable_usb)
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{
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uint8_t control_1, control_2;
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if (!ec_running())
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return;
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control_1 = ec_read(EC_DEVICE_CONTROL_1);
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control_2 = ec_read(EC_DEVICE_CONTROL_2);
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printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1);
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printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2);
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control_1 &= ~(EC_DEVICE_CONTROL_1_BT_RF_ON);
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control_1 |= EC_DEVICE_CONTROL_1_BOOMER_ON;
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control_2 &= ~(EC_DEVICE_CONTROL_2_WLAN_ON | EC_DEVICE_CONTROL_2_USB_ON);
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control_2 |= EC_DEVICE_CONTROL_2_MPI_ON;
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if (enable_usb)
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control_2 |= EC_DEVICE_CONTROL_2_USB_ON;
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ec_write(EC_DEVICE_CONTROL_1, control_1);
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ec_write(EC_DEVICE_CONTROL_2, control_2);
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printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1));
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printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2));
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}
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void mainboard_smi_sleep(const uint8_t slp_typ)
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{
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uint8_t control_1, control_2;
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if (slp_typ != ACPI_S5)
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return;
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if (!ec_running())
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return;
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control_1 = ec_read(EC_DEVICE_CONTROL_1);
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control_2 = ec_read(EC_DEVICE_CONTROL_2);
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printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1);
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printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2);
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control_1 &= ~(EC_DEVICE_CONTROL_1_BOOMER_ON);
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control_2 &= ~(EC_DEVICE_CONTROL_2_USB_ON | EC_DEVICE_CONTROL_2_MPI_ON);
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ec_write(EC_DEVICE_CONTROL_1, control_1);
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ec_write(EC_DEVICE_CONTROL_2, control_2);
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printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1));
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printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2));
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SIEMENS_CHILI_EC_H
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#define _SIEMENS_CHILI_EC_H
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void ec_enable_devices(bool enable_usb);
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#endif /* _SIEMENS_CHILI_EC_H */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include "ec.h"
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static void mainboard_dev_init(struct device *dev)
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{
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const bool enable_usb = CONFIG(BOARD_SIEMENS_CHILI_BASE);
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ec_enable_devices(enable_usb);
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_dev_init;
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <option.h>
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#include <soc/cnl_memcfg_init.h>
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#include <soc/gpio.h>
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#include <soc/romstage.h>
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#include "variant.h"
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static void mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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uint8_t vtd = 1;
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const struct cnl_mb_cfg cfg = {
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.spd = {
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[0] = { READ_SMBUS, { 0x50 << 1 } },
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[2] = { READ_SMBUS, { 0x52 << 1 } },
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},
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.rcomp_resistor = { 121, 75, 100 },
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.rcomp_targets = { 50, 25, 20, 20, 26 },
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.dq_pins_interleaved = 1,
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.vref_ca_config = 2,
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.ect = 0,
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};
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cannonlake_memcfg_init(&memupd->FspmConfig, &cfg);
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memupd->FspmConfig.EccSupport = 1;
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memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
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get_option(&vtd, "vtd");
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memupd->FspmTestConfig.VtdDisable = !vtd;
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get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading");
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mainboard_init();
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}
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _VARIANT_H_
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#define _VARIANT_H_
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const struct pad_config *variant_gpio_table(size_t *num);
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#endif /* _VARIANT_H_ */
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## SPDX-License-Identifier: GPL-2.0-only
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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Board name: Chili base board
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Binary file not shown.
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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/cannonlake
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "RMT" = "0"
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register "speed_shift_enable" = "1"
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 off end # PCIe x16
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device pci 01.1 off end # PCIe x8
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device pci 01.2 off end # PCIe x4
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA Thermal device
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device pci 05.0 off end # Imaging Processing Unit
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device pci 08.0 off end # Gaussian mixture model, Neural network accelerator
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # ISH
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device pci 14.0 on # USB xHCI
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C?
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711
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register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue
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register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue
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register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC?
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C?
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage?
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Shared SRAM
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device pci 14.3 off end # CNVi Wifi
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device pci 14.5 off end # SDCard
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on # Management Engine Interface 1
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register "HeciEnabled" = "1"
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end
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1" # HDD / SSD
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register "SataPortsEnable[1]" = "1" # ODD
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register "SataPortsEnable[3]" = "1" # HDD / SSD
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register "SataPortsDevSlp[0]" = "1" # M.2
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register "SataPortsDevSlp[2]" = "1" # HDD / SSD
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end
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on # PCI Express Port 5
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device pci 00.0 on end # x1 i219
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register "PcieRpEnable[4]" = "1"
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register "PcieClkSrcUsage[4]" = "0x70"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieRpSlotImplemented[4]" = "0"
|
||||
end
|
||||
device pci 1c.5 on # PCI Express Port 6
|
||||
device pci 00.0 on end # x1 i210
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieClkSrcUsage[5]" = "5"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
register "PcieRpSlotImplemented[5]" = "0"
|
||||
end
|
||||
device pci 1c.6 on # PCI Express Port 7
|
||||
device pci 00.0 on end # x1 M.2 (WLAN / BT)
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpSlotImplemented[6]" = "1"
|
||||
end
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 off end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1b.0 on # PCI Express Port 17
|
||||
device pci 00.0 on end # x4 M.2/M
|
||||
register "PcieRpEnable[16]" = "1"
|
||||
register "PcieClkSrcUsage[7]" = "16"
|
||||
register "PcieClkSrcClkReq[7]" = "7"
|
||||
register "PcieRpSlotImplemented[16]" = "1"
|
||||
end
|
||||
device pci 1b.1 off end # PCI Express Port 18
|
||||
device pci 1b.2 off end # PCI Express Port 19
|
||||
device pci 1b.3 off end # PCI Express Port 20
|
||||
device pci 1b.4 off end # PCI Express Port 21
|
||||
device pci 1b.5 off end # PCI Express Port 22
|
||||
device pci 1b.6 off end # PCI Express Port 23
|
||||
device pci 1b.7 off end # PCI Express Port 24
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on # LPC Interface
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 on end # GbE
|
||||
device pci 1f.7 off end # TraceHub
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(DP1, -- VGA (DVI-I)
|
||||
HDMI2, -- DVI-I
|
||||
DP3, -- DP++
|
||||
HDMI3, -- DP++
|
||||
eDP,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include "variant.h"
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE),
|
||||
/* GPP_A16 GPIO */ PAD_NC(GPP_A16, DN_20K),
|
||||
/* GPP_B4 GPIO */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
/* GPP_B5 GPIO */ PAD_NC(GPP_B5, NONE),
|
||||
/* GPP_B6 GPIO */ PAD_NC(GPP_B6, NONE),
|
||||
/* GPP_B8 GPIO */ PAD_NC(GPP_B8, NONE),
|
||||
/* GPP_B10 GPIO */ PAD_NC(GPP_B10, NONE),
|
||||
/* GPP_B11 GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP),
|
||||
/* GPP_B14 SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
/* GPP_B18 GPIO */ PAD_NC(GPP_B18, NONE),
|
||||
/* GPP_B22 GPIO */ PAD_NC(GPP_B22, NONE),
|
||||
/* GPP_C2 GPIO */ PAD_NC(GPP_C2, NONE),
|
||||
/* GPP_C5 GPIO */ PAD_NC(GPP_C5, NONE),
|
||||
/* GPP_C6 SML1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
/* GPP_C7 SML1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
/* GPP_C8 GPIO */ PAD_NC(GPP_C8, NONE),
|
||||
/* GPP_C9 GPIO */ PAD_NC(GPP_C9, NONE),
|
||||
/* GPP_C12 GPIO */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
/* GPP_C13 GPIO */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
/* GPP_C14 GPIO */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
/* GPP_C15 GPIO */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
/* GPP_C16 I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
/* GPP_C17 I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
/* GPP_C20 UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* GPP_C21 UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* GPP_C22 UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
/* GPP_C23 UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
|
||||
/* GPP_D1 GPIO */ PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
/* GPP_D2 GPIO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
/* GPP_D3 GPIO */ PAD_CFG_GPO(GPP_D3, 1, DEEP),
|
||||
/* GPP_D7 GPIO */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST),
|
||||
/* GPP_D8 GPIO */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST),
|
||||
/* GPP_D17 DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
/* GPP_D18 DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
/* GPP_D19 DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* GPP_D20 DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
/* GPP_D21 GPIO */ PAD_CFG_GPO(GPP_D21, 1, DEEP),
|
||||
/* GPP_D22 GPIO */ PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
/* GPP_G1 GPIO */ PAD_CFG_GPO(GPP_G1, 1, PLTRST),
|
||||
/* GPP_G2 GPIO */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST),
|
||||
/* GPP_G3 GPIO */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT),
|
||||
/* I2S1_SFRM GPIO */ PAD_NC(I2S1_SFRM, NONE),
|
||||
/* I2S1_TXD GPIO */ PAD_NC(I2S1_TXD, NONE),
|
||||
/* GPD0 BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1 ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
/* GPD7 GPIO */ PAD_CFG_GPO(GPD7, 0, RSMRST),
|
||||
/* GPP_K0 GPIO */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST),
|
||||
/* GPP_K1 GPIO */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST),
|
||||
/* GPP_K2 GPIO */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST),
|
||||
/* GPP_K3 GPIO */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST),
|
||||
/* GPP_K4 GPIO */ PAD_CFG_GPO(GPP_K4, 1, PWROK),
|
||||
/* GPP_K5 GPIO */ PAD_CFG_GPO(GPP_K5, 1, PWROK),
|
||||
/* GPP_K8 GPIO */ PAD_NC(GPP_K8, NONE),
|
||||
/* GPP_K9 GPIO */ PAD_NC(GPP_K9, NONE),
|
||||
/* GPP_K10 GPIO */ PAD_NC(GPP_K10, NONE),
|
||||
/* GPP_K11 GPIO */ PAD_NC(GPP_K11, NONE),
|
||||
/* GPP_K20 GPIO */ PAD_CFG_GPO(GPP_K20, 1, PLTRST),
|
||||
/* GPP_K21 GPIO */ PAD_NC(GPP_K21, NONE),
|
||||
/* GPP_H0 GPIO */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST),
|
||||
/* GPP_H2 GPIO */ PAD_NC(GPP_H2, NONE),
|
||||
/* GPP_H3 GPIO */ PAD_NC(GPP_H3, NONE),
|
||||
/* GPP_H10 GPIO */ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
/* GPP_H15 GPIO */ PAD_CFG_GPO(GPP_H15, 1, DEEP),
|
||||
/* GPP_H17 GPIO */ PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
/* GPP_E0 SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
|
||||
/* GPP_E1 GPIO */ PAD_NC(GPP_E1, NONE),
|
||||
/* GPP_E2 GPIO */ PAD_NC(GPP_E2, NONE),
|
||||
/* GPP_E4 SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
|
||||
/* GPP_E5 GPIO */ PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
/* GPP_E6 GPIO */ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
/* GPP_E8 SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
/* GPP_E9 USB2_OC0# */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1),
|
||||
/* GPP_E10 USB2_OC1# */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1),
|
||||
/* GPP_E11 USB2_OC2# */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1),
|
||||
/* GPP_E12 GPIO */ PAD_CFG_GPO(GPP_E12, 1, PLTRST),
|
||||
/* GPP_F1 GPIO */ PAD_NC(GPP_F1, NONE),
|
||||
/* GPP_F2 GPIO */ PAD_NC(GPP_F2, NONE),
|
||||
/* GPP_F3 GPIO */ PAD_NC(GPP_F3, NONE),
|
||||
/* GPP_F4 GPIO */ PAD_NC(GPP_F4, NONE),
|
||||
/* GPP_F5 GPIO */ PAD_CFG_GPO(GPP_F5, 1, PLTRST),
|
||||
/* GPP_F6 SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* GPP_F8 GPIO */ PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
/* GPP_F9 GPIO */ PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
/* GPP_F10 GPIO */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
|
||||
/* GPP_F13 GPIO */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
|
||||
/* GPP_F14 GPIO */ PAD_NC(GPP_F14, NONE),
|
||||
/* GPP_F15 USB2_OC4# */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1),
|
||||
/* GPP_F16 USB2_OC5# */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1),
|
||||
/* GPP_F17 USB2_OC6# */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1),
|
||||
/* GPP_F18 GPIO */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT),
|
||||
/* GPP_F19 eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* GPP_F20 eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* GPP_F21 eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* GPP_F22 DDPF_CTRLCLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* GPP_F23 DDPF_CTRLDATA */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
/* GPP_I0 DDPB_HPD0 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1),
|
||||
/* GPP_I1 DDPB_HPD1 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1),
|
||||
/* GPP_I2 DDPB_HPD2 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1),
|
||||
/* GPP_I3 DDPB_HPD3 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
|
||||
/* GPP_I4 EDP_HPD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
/* GPP_I5 DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
/* GPP_I6 DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
/* GPP_I7 DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
|
||||
/* GPP_I8 DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
|
||||
/* GPP_I9 DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1),
|
||||
/* GPP_I10 DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1),
|
||||
/* GPP_J2 n/a */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
/* GPP_J3 n/a */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1),
|
||||
/* GPP_J4 CNV_BRI_DT */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
/* GPP_J5 CNV_BRI_RSP */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1),
|
||||
/* GPP_J6 CNV_RGI_DT */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
/* GPP_J7 CNV_RGI_RSP */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
/* GPP_J8 CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
/* GPP_J9 CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
/* GPP_J10 n/a */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1),
|
||||
/* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
Loading…
Reference in New Issue