soc/intel/broadwell: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -39,6 +39,12 @@
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#define HPET_BASE_ADDRESS 0xfed00000
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#define GFXVT_BASE_ADDRESS 0xfed90000ULL
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#define GFXVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000ULL
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#define VTVC0_BASE_SIZE 0x1000
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#define ACPI_BASE_ADDRESS 0x1000
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#define ACPI_BASE_SIZE 0x100
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@ -86,4 +86,7 @@
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#define PMIR_CF9LOCK (1 << 31)
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#define PMIR_CF9GR (1 << 20)
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#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */
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#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */
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#endif
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@ -112,4 +112,9 @@
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#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5)
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#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6)
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#define PCH_IOAPIC_PCI_BUS 250
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#define PCH_IOAPIC_PCI_SLOT 31
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#define PCH_HPET_PCI_BUS 250
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#define PCH_HPET_PCI_SLOT 15
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#endif
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@ -74,6 +74,11 @@
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
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#define DMAR_LCKDN (1 << 31)
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#define PRSCAPDIS (1 << 2)
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#define MESEG_BASE 0x70 /* Management Engine Base. */
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#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
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@ -95,7 +100,9 @@
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#define MCHBAR_PEI_VERSION 0x5034
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#define BIOS_RESET_CPL 0x5da8
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#define GFXVTBAR 0x5400
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#define EDRAMBAR 0x5408
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#define VTVC0BAR 0x5410
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#define MCH_PAIR 0x5418
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#define GDXCBAR 0x5420
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@ -49,6 +49,10 @@ static void pch_enable_ioapic(struct device *dev)
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{
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u32 reg32;
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/* Assign unique bus/dev/fn for I/O APIC */
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pci_write_config16(dev, LPC_IBDF,
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PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
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set_ioapic_id(VIO_APIC_VADDR, 0x02);
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/* affirm full set of redirection table entries ("write once") */
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@ -67,6 +71,16 @@ static void pch_enable_ioapic(struct device *dev)
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io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
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}
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static void enable_hpet(struct device *dev)
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{
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size_t i;
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/* Assign unique bus/dev/fn for each HPET */
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for (i = 0; i < 8; ++i)
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pci_write_config16(dev, LPC_HnBDF(i),
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PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
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}
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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@ -436,6 +450,7 @@ static void lpc_init(struct device *dev)
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pch_pirq_init(dev);
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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enable_hpet(dev);
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/* Initialize power management */
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pch_power_options(dev);
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@ -47,5 +47,26 @@ static const struct reg_script systemagent_early_init_script[] = {
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void systemagent_early_init(void)
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{
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const bool vtd_capable =
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!(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE);
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reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script);
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if (vtd_capable) {
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/* setup BARs: zeroize top 32 bits; set enable bit */
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MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32;
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MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1;
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MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32;
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MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1;
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/* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */
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u32 reg32;
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reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS));
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write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS),
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reg32 | DMAR_LCKDN | PRSCAPDIS);
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/* lock VTVC0BAR policy cfg registers */
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reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS));
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write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS),
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reg32 | DMAR_LCKDN);
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}
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}
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@ -271,7 +271,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
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printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
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}
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static void mc_add_dram_resources(device_t dev)
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static void mc_add_dram_resources(device_t dev, int *resource_cnt)
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{
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unsigned long base_k, size_k;
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unsigned long touud_k;
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@ -327,7 +327,7 @@ static void mc_add_dram_resources(device_t dev)
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* The resource index starts low and should not meet or exceed
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* PCI_BASE_ADDRESS_0.
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*/
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index = 0;
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index = *resource_cnt;
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/* 0 - > 0xa0000 */
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base_k = 0;
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@ -373,18 +373,32 @@ static void mc_add_dram_resources(device_t dev)
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(0x100000 - 0xc0000) >> 10);
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chromeos_reserve_ram_oops(dev, index++);
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*resource_cnt = index;
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}
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static void systemagent_read_resources(device_t dev)
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{
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int index = 0;
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const bool vtd_capable =
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!(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
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/* Read standard PCI resources. */
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pci_dev_read_resources(dev);
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/* Add all fixed MMIO resources. */
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mc_add_fixed_mmio_resources(dev);
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/* Add VT-d MMIO resources if capable */
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if (vtd_capable) {
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mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
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GFXVT_BASE_SIZE / KiB);
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mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
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VTVC0_BASE_SIZE / KiB);
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}
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/* Calculate and add DRAM resources. */
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mc_add_dram_resources(dev);
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mc_add_dram_resources(dev, &index);
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}
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static void systemagent_init(struct device *dev)
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