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vendorcode/amd/opensil: Set up resource manager input block 

Tell the resource manager in openSIL to distribute the available IO and
MMIO ranges across the different PCI root bridges.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Arthur Heymans 2023-07-14 19:56:03 +02:00 committed by Felix Held
parent a595478428
commit 81ceea1592
1 changed files with 22 additions and 0 deletions
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22
src/vendorcode/amd/opensil/genoa_poc/ramstage.c
View File

@ -1,8 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <RcMgr/DfX/RcManager4-api.h>
#include <amdblocks/reset.h> #include <amdblocks/reset.h>
#include <bootstate.h> #include <bootstate.h>
#include <cbmem.h> #include <cbmem.h>
#include <cpu/cpu.h>
#include <xSIM-api.h> #include <xSIM-api.h>
#include "opensil_console.h" #include "opensil_console.h"
@ -38,6 +40,24 @@ static void SIL_STATUS_report(const char *function, const int status)
printk(log_level, "%s returned %d (%s)\n", function, status, error_string); printk(log_level, "%s returned %d (%s)\n", function, status, error_string);
} }
static void setup_rc_manager_default(void)
{
DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager, 0);
/* Let openSIL distribute the resources to the different PCI roots */
rc_mgr_input_block->SetRcBasedOnNv = false;
/* Currently 1P is the only supported configuration */
rc_mgr_input_block->SocketNumber = 1;
rc_mgr_input_block->RbsPerSocket = 4; /* PCI root bridges per socket */
rc_mgr_input_block->McptEnable = true;
rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB;
rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB;
/* MmioAbove4GLimit will be adjusted down in openSIL */
rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size());
rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0;
}
static void setup_opensil(void *unused) static void setup_opensil(void *unused)
{ {
const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService); const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService);
@ -48,6 +68,8 @@ static void setup_opensil(void *unused)
/* We run all openSIL timepoints in the same stage so using TP1 as argument is fine. */ /* We run all openSIL timepoints in the same stage so using TP1 as argument is fine. */
const SIL_STATUS assign_mem_ret = xSimAssignMemoryTp1(buf, mem_req); const SIL_STATUS assign_mem_ret = xSimAssignMemoryTp1(buf, mem_req);
SIL_STATUS_report("xSimAssignMemory", assign_mem_ret); SIL_STATUS_report("xSimAssignMemory", assign_mem_ret);
setup_rc_manager_default();
} }
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, setup_opensil, NULL); BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, setup_opensil, NULL);