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lynxpoint: Fix early EHCI BAR programming 

LynxPoint LP has only EHCI controller #1.
Change EHCI #2 to different BAR from EHCI #1.

Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.

Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3472
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-06-15 12:30:13 +03:00 committed by Ronald G. Minnich
parent dbc6fcd021
commit 81d3d7d001
1 changed files with 13 additions and 17 deletions
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30
src/southbridge/intel/lynxpoint/early_usb.c
View File

@ -34,23 +34,19 @@
* The BAR will be re-assigned during device
* enumeration so these are only temporary.
*/
static void enable_usb_bar_on_device(device_t dev, u32 bar)
{
u32 cmd;
pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar);
cmd = pci_read_config32(dev, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, cmd);
}
void enable_usb_bar(void)
{
device_t usb0 = PCH_EHCI1_DEV;
device_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
/* USB Controller 1 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 1 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
#if !CONFIG_INTEL_LYNXPOINT_LP
enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
#endif
}