soc/intel/apollolake: Add `GPE0_STS_BIT` macro
The datasheet indicates that this bit is reserved. However, subsequent patches need to use this macro in common code, or else builds fail. To iron out this difference, mask out the bit in `soc_get_smi_status`, so that common code always sees it as zero. Finally, add an entry for the bit in `smi_sts_bits` for debugging usage, noting that it is reserved. Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -108,6 +108,7 @@
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#define MC_SMI_STS_BIT 12
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#define MC_SMI_STS_BIT 12
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#define GPIO_UNLOCK_SMI_STS_BIT 11
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#define GPIO_UNLOCK_SMI_STS_BIT 11
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#define GPIO_STS_BIT 10
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#define GPIO_STS_BIT 10
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#define GPE0_STS_BIT 9 /* Datasheet says this is reserved */
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#define PM1_STS_BIT 8
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#define PM1_STS_BIT 8
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#define SWSMI_TMR_STS_BIT 6
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#define SWSMI_TMR_STS_BIT 6
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#define APM_STS_BIT 5
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#define APM_STS_BIT 5
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@ -48,6 +48,7 @@ const char *const *soc_smi_sts_array(size_t *a)
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[APM_STS_BIT] = "APM",
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[APM_STS_BIT] = "APM",
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[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
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[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
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[PM1_STS_BIT] = "PM1",
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[PM1_STS_BIT] = "PM1",
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[GPE0_STS_BIT] = "GPE0 (reserved)",
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[GPIO_STS_BIT] = "GPIO_SMI",
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[GPIO_STS_BIT] = "GPIO_SMI",
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[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI",
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[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI",
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[MC_SMI_STS_BIT] = "MCSMI",
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[MC_SMI_STS_BIT] = "MCSMI",
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@ -86,7 +87,11 @@ uint32_t soc_get_smi_status(uint32_t generic_sts)
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generic_sts |= (1 << PM1_STS_BIT);
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generic_sts |= (1 << PM1_STS_BIT);
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}
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}
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return generic_sts;
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/*
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* GPE0_STS is reserved in APL/GLK datasheets. For compatibility
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* with common code, mask it out so that it is always zero.
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*/
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return generic_sts & ~(1 << GPE0_STS_BIT);
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}
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}
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const char *const *soc_tco_sts_array(size_t *a)
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const char *const *soc_tco_sts_array(size_t *a)
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