sb/intel/common/smi.c: Remove unused functions
Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
parent
97c7c6bbb6
commit
81e9b8ee67
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@ -17,11 +17,8 @@ void bsp_init_and_start_aps(struct bus *cpu_bus);
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/* These helpers are for performing SMM relocation. */
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/* These helpers are for performing SMM relocation. */
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void southbridge_smm_init(void);
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void southbridge_smm_init(void);
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void southbridge_trigger_smi(void);
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void southbridge_clear_smi_status(void);
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u32 northbridge_get_tseg_base(void);
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u32 northbridge_get_tseg_base(void);
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u32 northbridge_get_tseg_size(void);
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u32 northbridge_get_tseg_size(void);
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int cpu_get_apic_id_map(int *apic_id_map);
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void northbridge_write_smram(u8 smram);
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void northbridge_write_smram(u8 smram);
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bool cpu_has_alternative_smrr(void);
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bool cpu_has_alternative_smrr(void);
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@ -100,60 +100,6 @@ static void write_smrr(struct smm_relocation_params *relo_params)
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}
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}
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}
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}
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/* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here. */
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static void asmlinkage cpu_smm_do_relocation(void *arg)
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{
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em64t101_smm_state_save_area_t *save_state;
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params;
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const struct smm_module_params *p;
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const struct smm_runtime *runtime;
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int cpu;
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p = arg;
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runtime = p->runtime;
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relo_params = p->arg;
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cpu = p->cpu;
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if (cpu >= CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Invalid CPU number assigned in SMM stub: %d\n", cpu);
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return;
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}
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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/* All threads need to set IEDBASE and SMBASE in the save state area.
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* Since one thread runs at a time during the relocation the save state
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* is the same for all cpus. */
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save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
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runtime->save_state_size);
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/* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num. */
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save_state->smbase = relo_params->smram_base -
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cpu * runtime->save_state_size;
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if (CONFIG_IED_REGION_SIZE != 0) {
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save_state->iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
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save_state->smbase, save_state->iedbase, save_state);
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} else {
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printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n",
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save_state->smbase, save_state);
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}
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/* Write SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0)
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write_smrr(relo_params);
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southbridge_clear_smi_status();
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}
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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{
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/* All range registers are aligned to 4KiB */
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/* All range registers are aligned to 4KiB */
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@ -202,33 +148,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
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}
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}
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}
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}
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static int install_relocation_handler(int *apic_id_map, int num_cpus,
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struct smm_relocation_params *relo_params)
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{
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/* The default SMM entry happens serially at the default location.
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* Therefore, there is only 1 concurrent save state area. Set the
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* stack size to the save state size, and call into the
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* do_relocation handler. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = 1,
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.handler = &cpu_smm_do_relocation,
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.handler_arg = (void *)relo_params,
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};
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default_smm_area = backup_default_smm_area();
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if (smm_setup_relocation_handler(&smm_params))
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return -1;
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int i;
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for (i = 0; i < num_cpus; i++)
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smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i];
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return 0;
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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static void setup_ied_area(struct smm_relocation_params *params)
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{
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{
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char *ied_base;
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char *ied_base;
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@ -248,94 +167,6 @@ static void setup_ied_area(struct smm_relocation_params *params)
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memset(ied_base + (1 << 20), 0, (32 << 10));
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memset(ied_base + (1 << 20), 0, (32 << 10));
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}
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}
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static int install_permanent_handler(int *apic_id_map, int num_cpus,
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struct smm_relocation_params *relo_params)
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{
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/* There are num_cpus concurrent stacks and num_cpus concurrent save
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* state areas. Lastly, set the stack size to the save state size. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = num_cpus,
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};
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printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
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relo_params->smram_base);
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if (smm_load_module((void *)relo_params->smram_base,
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relo_params->smram_size, &smm_params))
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return -1;
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int i;
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for (i = 0; i < num_cpus; i++)
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smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i];
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return 0;
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}
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static int cpu_smm_setup(void)
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{
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int num_cpus;
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int apic_id_map[CONFIG_MAX_CPUS];
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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fill_in_relocation_params(&smm_reloc_params);
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/* enable the SMM memory window */
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northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG);
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if (CONFIG_IED_REGION_SIZE != 0)
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setup_ied_area(&smm_reloc_params);
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num_cpus = cpu_get_apic_id_map(apic_id_map);
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if (num_cpus > CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
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num_cpus, CONFIG_MAX_CPUS);
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}
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if (install_relocation_handler(apic_id_map, num_cpus,
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&smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
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return -1;
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}
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if (install_permanent_handler(apic_id_map, num_cpus,
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&smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
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return -1;
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}
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/* Ensure the SMM handlers hit DRAM before performing first SMI. */
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/* TODO(adurbin): Is this really needed? */
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wbinvd();
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/* close the SMM memory window and enable normal SMM */
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northbridge_write_smram(G_SMRAME | C_BASE_SEG);
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return 0;
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}
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void smm_init(void)
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{
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/* Return early if CPU SMM setup failed. */
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if (cpu_smm_setup())
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return;
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southbridge_smm_init();
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/* Initiate first SMI to kick off SMM-context relocation. Note: this
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* SMI being triggered here queues up an SMI in the APs which are in
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* wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
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* at the SMM_DEFAULT_BASE before jumping to startup vector. */
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southbridge_trigger_smi();
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printk(BIOS_DEBUG, "Relocation complete.\n");
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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void smm_init_completion(void)
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void smm_init_completion(void)
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{
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{
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restore_default_smm_area(default_smm_area);
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restore_default_smm_area(default_smm_area);
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@ -104,38 +104,6 @@ void southbridge_smm_init(void)
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write_pmbase32(SMI_EN, smi_en);
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write_pmbase32(SMI_EN, smi_en);
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}
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}
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void southbridge_trigger_smi(void)
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{
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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outb(0x00, 0xb2);
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}
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void southbridge_clear_smi_status(void)
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{
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/* Clear SMI status */
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reset_smi_status();
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/* Clear PM1 status */
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reset_pm1_status();
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/* Set EOS bit so other SMIs can occur. */
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smi_set_eos();
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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{
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/*
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/*
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