mainboard/google/poppy: Add support for cr50 SPI TPM

Put all configs required for enabling cr50 SPI TPM on poppy under
POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI
TPM on this board.

Also, add required callback for irq status and devicetree config for
GSPI0.

BUG=b:36873582

Change-Id: I67793093c006c1325fc16f669a96126525f83243
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/poppy/Kconfig

@@ -48,3 +48,16 @@ config INCLUDE_NHLT_BLOBS
 	select NHLT_MAX98927
 	select NHLT_RT5663
 endif
+
+# Select this option to enable use of cr50 SPI TPM on poppy.
+# This option is disabled by default.
+config POPPY_USE_SPI_TPM
+	bool
+	default n
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select MAINBOARD_HAS_TPM2
+	select SPI_TPM
+	select TPM2
+
+config DRIVER_TPM_SPI_BUS
+	default 0x1

src/mainboard/google/poppy/chromeos.c

@@ -13,9 +13,12 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
 #include <gpio.h>
 #include <rules.h>
+#include <soc/gpe.h>
 #include <soc/gpio.h>
+#include <tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 #include "gpio.h"
@@ -53,3 +56,8 @@ void mainboard_chromeos_acpi_generate(void)
 {
 	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
 }
+
+int tis_plat_irq_status(void)
+{
+	return acpi_get_gpe(GPE0_DW2_00);
+}

src/mainboard/google/poppy/devicetree.cb

@@ -157,6 +157,13 @@ chip soc/intel/skylake
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"		# Camera
 	register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"		# Audio
 
+	# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
+	# communication before memory is up.
+	register "gspi[0]" = "{
+		 .speed_mhz = 1,
+		 .early_init = 1,
+	}"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,