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amd/stoneyridge: Use generic fixed MTRR setup 

Add the X86_AMD_FIXED_MTRRS select back to Kconfig.  This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.

Remove the setup from model_15_init.c because this is duplicated
functionality.

BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT

Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-10-20 12:36:35 -06:00 committed by Aaron Durbin
parent c0dbedac43
commit 82145a1275
2 changed files with 1 additions and 37 deletions
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1
src/soc/amd/stoneyridge/Kconfig
View File

@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32 select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32
select X86_AMD_FIXED_MTRRS
select ACPI_AMD_HARDWARE_SLEEP_VALUES select ACPI_AMD_HARDWARE_SLEEP_VALUES
select COLLECT_TIMESTAMPS_NO_TSC select COLLECT_TIMESTAMPS_NO_TSC
select DRIVERS_I2C_DESIGNWARE select DRIVERS_I2C_DESIGNWARE

37
src/soc/amd/stoneyridge/model_15_init.c
View File

@ -16,7 +16,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <string.h> #include <string.h>
@ -26,22 +25,9 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h> #include <cpu/amd/amdfam15.h>
#include <arch/acpi.h> #include <arch/acpi.h>
static void msr_rw_dram(unsigned int reg)
{
#define RW_DRAM (MTRR_READ_MEM | MTRR_WRITE_MEM)
#define ALL_RW_DRAM ((RW_DRAM << 24) | (RW_DRAM << 16) | \
(RW_DRAM << 8) | (RW_DRAM))
msr_t mtrr = rdmsr(reg);
mtrr.hi |= ALL_RW_DRAM;
mtrr.lo |= ALL_RW_DRAM;
wrmsr(reg, mtrr);
}
static void model_15_init(device_t dev) static void model_15_init(device_t dev)
{ {
printk(BIOS_DEBUG, "Model 15 Init.\n"); printk(BIOS_DEBUG, "Model 15 Init.\n");
@ -49,29 +35,6 @@ static void model_15_init(device_t dev)
int i; int i;
msr_t msr; msr_t msr;
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* Send all but A0000-BFFFF to DRAM */
msr_rw_dram(MTRR_FIX_64K_00000);
msr_rw_dram(MTRR_FIX_16K_80000);
for (i = MTRR_FIX_4K_C0000 ; i <= MTRR_FIX_4K_F8000 ; i++)
msr_rw_dram(i);
/* Hide RdDram and WrDram bits, and clear Tom2ForceMemTypeWB */
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_TOM2WB;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;