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ACPI: Remove CONFIG_GENERATE_ACPI_TABLES 

As currently many systems would be barely functional without ACPI,
always generate ACPI tables if supported.

Change-Id: I372dbd03101030c904dab153552a1291f3b63518
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4609
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Vladimir Serbinenko 2014-01-03 15:55:40 +01:00
parent 0e64617d7d
commit 822bc65b0e
63 changed files with 48 additions and 1286 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/Kconfig
View File

@ -438,8 +438,6 @@ config HAVE_ACPI_TABLES
help
This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
is configurable by the user via GENERATE_ACPI_TABLES.
config HAVE_MP_TABLE
bool
@ -477,15 +475,6 @@ config PER_DEVICE_ACPI_TABLES
menu "System tables"
config GENERATE_ACPI_TABLES
prompt "Generate ACPI tables" if HAVE_ACPI_TABLES
bool
default HAVE_ACPI_TABLES
help
Generate ACPI tables for this board.
If unsure, say Y.
config GENERATE_MP_TABLE
prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
bool

2
src/arch/x86/Makefile.inc
View File

@ -278,7 +278,7 @@ endif
ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/reset.c),)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c
endif
ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y)
ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl
ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt2.asl),)

4
src/arch/x86/boot/Makefile.inc
View File

@ -14,9 +14,9 @@ ramstage-y += tables.c
ramstage-y += cbmem.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h

2
src/arch/x86/boot/smbios.c
View File

@ -169,7 +169,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
BIOS_CHARACTERISTICS_UPGRADEABLE;
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
#endif
t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;

2
src/arch/x86/boot/tables.c
View File

@ -108,7 +108,7 @@ void write_tables(void)
}
#endif /* CONFIG_GENERATE_MP_TABLE */
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
#if CONFIG_DYNAMIC_CBMEM
#define MAX_ACPI_SIZE (144 * 1024)
#else

8
src/arch/x86/include/arch/acpi.h
View File

@ -27,8 +27,6 @@
#ifndef __ASM_ACPI_H
#define __ASM_ACPI_H
#if CONFIG_GENERATE_ACPI_TABLES
#include <stdint.h>
#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
@ -581,12 +579,6 @@ unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current);
/* cpu/intel/speedstep/acpi.c */
void generate_cpu_entries(void);
#else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start)
#endif /* CONFIG_GENERATE_ACPI_TABLES */
static inline int acpi_s3_resume_allowed(void)
{
return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME);

2
src/cpu/amd/model_fxx/Makefile.inc
View File

@ -4,4 +4,4 @@ romstage-y += ../../x86/mtrr/earlymtrr.c
ramstage-y += model_fxx_init.c
ramstage-y += model_fxx_update_microcode.c
ramstage-y += processor_name.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c

2
src/cpu/intel/fsp_model_206ax/Makefile.inc
View File

@ -1,7 +1,7 @@
ramstage-y += model_206ax_init.c
subdirs-y += ../../x86/name
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

2
src/cpu/intel/fsp_model_406dx/Makefile.inc
View File

@ -20,7 +20,7 @@
ramstage-y += model_406dx_init.c
subdirs-y += ../../x86/name
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c

2
src/cpu/intel/haswell/Makefile.inc
View File

@ -3,7 +3,7 @@ ramstage-y += tsc_freq.c
romstage-y += romstage.c
romstage-y += tsc_freq.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c

2
src/cpu/intel/model_2065x/Makefile.inc
View File

@ -13,7 +13,7 @@ ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

2
src/cpu/intel/model_206ax/Makefile.inc
View File

@ -1,7 +1,7 @@
ramstage-y += model_206ax_init.c
subdirs-y += ../../x86/name
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

3
src/cpu/intel/speedstep/Makefile.inc
View File

@ -1,2 +1 @@
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c
ramstage-$(CONFIG_CPU_INTEL_MODEL_1067X) += speedstep.c
ramstage-y += acpi.c speedstep.c

2
src/include/device/device.h
View File

@ -57,7 +57,7 @@ struct device_operations {
int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t);
#endif
#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES)
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES)
unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp);
void (*acpi_fill_ssdt_generator)(void);
void (*acpi_inject_dsdt_generator)(void);

4
src/lib/coreboot_table.c
View File

@ -32,7 +32,7 @@
#include <cbmem.h>
#include <bootmem.h>
#if CONFIG_CHROMEOS
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
#include <arch/acpi.h>
#endif
#include <vendorcode/google/chromeos/chromeos.h>
@ -168,7 +168,7 @@ static void lb_gpios(struct lb_header *header)
static void lb_vdat(struct lb_header *header)
{
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
struct lb_range *vdat;
vdat = (struct lb_range *)lb_new_record(header);

58
src/mainboard/advansus/a785e-i/mptable.c
View File

@ -75,64 +75,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

58
src/mainboard/amd/bimini_fam10/mptable.c
View File

@ -79,64 +79,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

51
src/mainboard/amd/dbm690t/mptable.c
View File

@ -97,57 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/amd/mahogany/mptable.c
View File

@ -98,63 +98,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

82
src/mainboard/amd/mahogany_fam10/mptable.c
View File

@ -97,88 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* changes added to match acpi tables */
PCI_INT(0x0, 0x02, 0x0, 0x12);
PCI_INT(0x0, 0x03, 0x0, 0x13);
PCI_INT(0x0, 0x04, 0x0, 0x10);
PCI_INT(0x0, 0x09, 0x0, 0x11);
PCI_INT(0x0, 0x0A, 0x0, 0x12);
PCI_INT(0x0, 0x12, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x3, 0x13);
PCI_INT(0x0, 0x13, 0x2, 0x10);
PCI_INT(0x0, 0x13, 0x2, 0x11);
PCI_INT(0x0, 0x14, 0x1, 0x11);
PCI_INT(0x0, 0x14, 0x3, 0x13);
PCI_INT(0x1, 0x05, 0x2, 0x10);
PCI_INT(0x1, 0x05, 0x3, 0x11);
PCI_INT(0x2, 0x00, 0x0, 0x12);
PCI_INT(0x2, 0x00, 0x1, 0x13);
PCI_INT(0x2, 0x00, 0x2, 0x10);
PCI_INT(0x2, 0x00, 0x3, 0x11);
/* RS780 PCI to PCI bridge (PCIE port 4) */
PCI_INT(0x0, 0x09, 0x0, 0x11);
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x2, 0x12);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */
PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */
/* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); *//* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
/* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
/* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */
PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */
/* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

51
src/mainboard/amd/pistachio/mptable.c
View File

@ -97,57 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/amd/tilapia_fam10/mptable.c
View File

@ -97,63 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/asrock/939a785gmh/mptable.c
View File

@ -96,63 +96,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/asus/m4a78-em/mptable.c
View File

@ -97,63 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/asus/m4a785-m/mptable.c
View File

@ -97,63 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

58
src/mainboard/asus/m5a88-v/mptable.c
View File

@ -75,64 +75,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

58
src/mainboard/avalue/eax-785e/mptable.c
View File

@ -76,64 +76,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x14, 0x4, 0x11);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);

8
src/mainboard/emulation/qemu-i440fx/fw_cfg.c
View File

@ -20,9 +20,7 @@
#include <smbios.h>
#include <console/console.h>
#include <arch/io.h>
#if CONFIG_GENERATE_ACPI_TABLES
# include <arch/acpigen.h>
#endif
#include <arch/acpigen.h>
#include "fw_cfg.h"
#include "fw_cfg_if.h"
@ -123,8 +121,6 @@ int fw_cfg_max_cpus(void)
/* ---------------------------------------------------------------------- */
#if CONFIG_GENERATE_ACPI_TABLES
/*
* Starting with release 1.7 qemu provides acpi tables via fw_cfg.
* Main advantage is that new (virtual) hardware which needs acpi
@ -313,8 +309,6 @@ err:
return 0;
}
#endif /* CONFIG_GENERATE_ACPI_TABLES */
/* ---------------------------------------------------------------------- */
/* pick up smbios information from fw_cfg */

57
src/mainboard/gigabyte/ma785gm/mptable.c
View File

@ -97,63 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/gigabyte/ma785gmt/mptable.c
View File

@ -97,63 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/gigabyte/ma78gm/mptable.c
View File

@ -97,63 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

82
src/mainboard/iei/kino-780am2-fam10/mptable.c
View File

@ -97,88 +97,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* changes added to match acpi tables */
PCI_INT(0x0, 0x02, 0x0, 0x12);
PCI_INT(0x0, 0x03, 0x0, 0x13);
PCI_INT(0x0, 0x04, 0x0, 0x10);
PCI_INT(0x0, 0x09, 0x0, 0x11);
PCI_INT(0x0, 0x0A, 0x0, 0x12);
PCI_INT(0x0, 0x12, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x3, 0x13);
PCI_INT(0x0, 0x13, 0x2, 0x10);
PCI_INT(0x0, 0x13, 0x2, 0x11);
PCI_INT(0x0, 0x14, 0x1, 0x11);
PCI_INT(0x0, 0x14, 0x3, 0x13);
PCI_INT(0x1, 0x05, 0x2, 0x10);
PCI_INT(0x1, 0x05, 0x3, 0x11);
PCI_INT(0x2, 0x00, 0x0, 0x12);
PCI_INT(0x2, 0x00, 0x1, 0x13);
PCI_INT(0x2, 0x00, 0x2, 0x10);
PCI_INT(0x2, 0x00, 0x3, 0x11);
/* RS780 PCI to PCI bridge (PCIE port 4) */
PCI_INT(0x0, 0x09, 0x0, 0x11);
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x2, 0x12);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */
PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */
/* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); */ /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
/* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
/* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */
PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */
/* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

57
src/mainboard/jetway/pa78vm5/mptable.c
View File

@ -98,63 +98,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

51
src/mainboard/kontron/kt690/mptable.c
View File

@ -96,57 +96,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

3
src/mainboard/lenovo/x200/mainboard.c
View File

@ -33,11 +33,8 @@
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#if CONFIG_GENERATE_ACPI_TABLES
#include "cstates.c" /* Include it, as the linker won't find
the overloaded weak function in there. */
#endif
const char *smbios_mainboard_bios_version(void)
{

2
src/mainboard/roda/rk9/mainboard.c
View File

@ -27,10 +27,8 @@
#include <pc80/keyboard.h>
#include <ec/acpi/ec.h>
#if CONFIG_GENERATE_ACPI_TABLES
#include "cstates.c" /* Include it, as the linker won't find
the overloaded weak function in there. */
#endif
static void ec_setup(void)
{

41
src/mainboard/supermicro/h8scm_fam10/mptable.c
View File

@ -107,28 +107,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
//PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x2, 0x10);
/* on board NIC & Slot PCIE. */
/* configuration B doesnt need dev 5,6,7 */
/*
@ -149,25 +127,6 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sp5100+1, 12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sp5100+1, 13); /* card behind dev12 */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

51
src/mainboard/technexion/tim5690/mptable.c
View File

@ -96,57 +96,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

51
src/mainboard/technexion/tim8690/mptable.c
View File

@ -96,57 +96,6 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);

2
src/northbridge/amd/agesa/family10/Makefile.inc
View File

@ -19,4 +19,4 @@
ramstage-y += northbridge.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl

2
src/northbridge/amd/agesa/family12/Makefile.inc
View File

@ -24,4 +24,4 @@ ramstage-y += northbridge.c
ramstage-y += fam12_callouts.c
ramstage-y += dimmSpd.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl

14
src/northbridge/amd/amdfam10/Makefile.inc
View File

@ -1,13 +1,13 @@
ramstage-y += northbridge.c
ramstage-y += misc_control.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr1.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr2.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr3.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr4.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr1.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr2.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr3.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr4.asl
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += sspr5.asl
ramstage-y += get_pci1234.c

2
src/northbridge/amd/amdk8/Makefile.inc
View File

@ -1,7 +1,7 @@
ramstage-y += northbridge.c
ramstage-y += misc_control.c
ramstage-y += get_sblk_pci1234.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
# Enable this if you want to check the values of the PCI routing registers.
# Call show_all_routes() anywhere amdk8.h is included.

2
src/northbridge/intel/fsp_rangeley/Makefile.inc
View File

@ -22,7 +22,7 @@ subdirs-y += fsp
ramstage-y += northbridge.c
ramstage-y += raminit.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
ramstage-y += port_access.c
romstage-y += raminit.c

2
src/northbridge/intel/fsp_sandybridge/Makefile.inc
View File

@ -22,7 +22,7 @@ subdirs-y += fsp
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
romstage-y += raminit.c
romstage-y += early_init.c

2
src/northbridge/intel/gm45/Makefile.inc
View File

@ -31,7 +31,7 @@ romstage-y += pm.c
romstage-y += ram_calc.c
romstage-$(CONFIG_IOMMU) += iommu.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
ramstage-y += ram_calc.c
ramstage-y += northbridge.c

2
src/northbridge/intel/haswell/Makefile.inc
View File

@ -21,7 +21,7 @@ ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
ramstage-y += mrccache.c
ramstage-y += minihd.c

2
src/northbridge/intel/i945/Makefile.inc
View File

@ -20,7 +20,7 @@
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
romstage-y += raminit.c

2
src/northbridge/intel/nehalem/Makefile.inc
View File

@ -21,7 +21,7 @@ ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
ramstage-y += ../sandybridge/mrccache.c
romstage-y += ram_calc.c

2
src/northbridge/intel/sandybridge/Makefile.inc
View File

@ -23,7 +23,7 @@ ramstage-y += gma.c
ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
ramstage-y += mrccache.c
romstage-y += ram_calc.c

2
src/northbridge/intel/sch/Makefile.inc
View File

@ -20,4 +20,4 @@
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-y += port_access.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c

2
src/northbridge/intel/sch/acpi.c
View File

@ -66,9 +66,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
if (!pciexbar)
return current;
#if CONFIG_GENERATE_ACPI_TABLES
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
#endif
return current;
}

2
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@ -42,7 +42,7 @@ ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sd.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c

4
src/southbridge/amd/amd8111/acpi.c
View File

@ -89,7 +89,7 @@ static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buf
}
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
unsigned pm_base;
#endif
@ -161,7 +161,7 @@ static void acpi_init(struct device *dev)
(on*12)+(on>>1),(on&1)*5);
}
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
pm_base = pci_read_config16(dev, 0x58) & 0xff00;
printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
#endif

2
src/southbridge/amd/cimx/sb800/Makefile.inc
View File

@ -32,7 +32,7 @@ ramstage-y += reset.c
ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c
ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c

2
src/southbridge/amd/sb700/Makefile.inc
View File

@ -7,7 +7,7 @@ ramstage-y += ide.c
ramstage-y += sata.c
ramstage-y += hda.c
ramstage-y += pci.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
romstage-y += reset.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c

2
src/southbridge/amd/sb800/Makefile.inc
View File

@ -7,7 +7,7 @@ ramstage-y += sata.c
ramstage-y += hda.c
ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c

2
src/southbridge/intel/fsp_rangeley/Makefile.inc
View File

@ -29,7 +29,7 @@ ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-y += spi.c
ramstage-y += smbus.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += acpi.c
romstage-y += early_usb.c early_smbus.c gpio.c reset.c early_spi.c early_init.c
romstage-y += romstage.c

4
src/southbridge/intel/i82371eb/Makefile.inc
View File

@ -24,8 +24,8 @@ ramstage-y += ide.c
ramstage-y += usb.c
ramstage-y += smbus.c
ramstage-y += reset.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
romstage-y += early_pm.c

2
src/southbridge/nvidia/ck804/Makefile.inc
View File

@ -13,7 +13,7 @@ ramstage-y += ht.c
ramstage-y += reset.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c

2
src/southbridge/nvidia/mcp55/Makefile.inc
View File

@ -11,7 +11,7 @@ ramstage-y += smbus.c
ramstage-y += usb2.c
ramstage-y += usb.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c

4
src/southbridge/nvidia/mcp55/smbus.c
View File

@ -93,7 +93,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
unsigned pm_base;
#endif
@ -112,7 +112,7 @@ static void mcp55_sm_read_resources(device_t dev)
static void mcp55_sm_init(device_t dev)
{
#if CONFIG_GENERATE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
struct resource *res;
res = find_resource(dev, 0x60);

2
src/southbridge/via/vt8237r/Makefile.inc
View File

@ -24,6 +24,6 @@ ramstage-y += lpc.c
ramstage-y += sata.c
ramstage-y += usb.c
ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c