intel/skylake: Add USB2 port config for max settings
Add a new USB2_PORT_MAX with the max possible settings (56mV) for the TX and Pre-emphasis bias values. Also fix the settings for the detachable tablet config to match the skylake HSIO tuning guide as it was incorrect before. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Id9ccc683fe92c962095347e0d1a0afeb082c821f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5d56831e75f98a3c75ed333e4b79b1a37f14792 Original-Change-Id: Ia2e3e93236f1463201f83a1cae28349de2836110 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308729 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12203 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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src/soc/intel/skylake/include/soc
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@ -65,6 +65,15 @@ struct usb2_port_config {
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* - Internal device down
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* - Internal device down
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*/
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*/
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/* Max TX and Pre-emp settings */
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#define USB2_PORT_MAX { \
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.enable = 1, \
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.tx_bias = USB2_BIAS_56MV, \
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.tx_emp_enable = USB2_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_56MV, \
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
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}
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/* 11.5"-12" */
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/* 11.5"-12" */
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#define USB2_PORT_LONG { \
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#define USB2_PORT_LONG { \
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.enable = 1, \
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.enable = 1, \
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@ -140,10 +149,10 @@ struct usb2_port_config {
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/* 2:1 Detachable, 2"-4" on tablet + 2"-4" on base */
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/* 2:1 Detachable, 2"-4" on tablet + 2"-4" on base */
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#define USB2_PORT_DETACHABLE_TABLET { \
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#define USB2_PORT_DETACHABLE_TABLET { \
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.enable = 1, \
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.enable = 1, \
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.tx_bias = USB2_BIAS_17MV, \
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.tx_bias = USB2_BIAS_56MV, \
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.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
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.tx_emp_enable = USB2_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_45MV, \
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.pre_emp_bias = USB2_BIAS_56MV, \
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.pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
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}
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}
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struct usb3_port_config {
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struct usb3_port_config {
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