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soc/intel/xeon_sp/spr: Add RMT config 

This commit adds a configuration option to enable RMT in the coreboot
build for the Intel Xeon SP SPR platform.

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Naresh Solanki 2023-05-24 11:24:28 +02:00 committed by Felix Held
parent a47dc10ea5
commit 82390fad49
2 changed files with 13 additions and 0 deletions
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6
src/soc/intel/xeon_sp/spr/Kconfig
View File

@ -182,4 +182,10 @@ config ENABLE_IO_MARGINING
ASPM. This option is intended for debugging and validation and
should normally be disabled.
config ENABLE_RMT
bool "Enable RMT"
default n
help
Enable Rank Margining Tool. This option is intended for debugging and
validation and should normally be disabled.
endif

7
src/soc/intel/xeon_sp/spr/romstage.c
View File

@ -217,6 +217,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mupd->FspmConfig.KtiLinkL1En = 0;
mupd->FspmConfig.KtiLinkL0pEn = 0;
}
if (CONFIG(ENABLE_RMT)) {
printk(BIOS_INFO, "RMT Enabled.\n");
mupd->FspmConfig.EnableRMT = 0x1;
/* Set FSP debug message to Max for RMT logs */
mupd->FspmConfig.serialDebugMsgLvl = 0x3;
}
}
static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)