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vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9 

Update the shared AGESA headers to 1.3.0.9.

This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated
to the same version.

BUG=b:72679320
TEST=build and boot Grunt

Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marc Jones 2018-01-25 17:05:46 -07:00 committed by Marc Jones
parent 0876caa473
commit 823dbde2ab
9 changed files with 89 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/vendorcode/amd/pi/00670F00/AGESA.h
View File

@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -1799,6 +1799,14 @@ typedef struct {
_4BYTE_ALIGN UINT32 NextBlockOffset; ///< Size of the whole device save context
} DEVICE_BLOCK_HEADER;
///===============================================================================
/// CPU_VREF_OVERRIDE
///
typedef struct _CPU_VREF_OVERRIDE{
IN UINT8 VrefOp; ///< Operater to adjust VrefHspeed
IN UINT8 VrefOffset; ///< Offset to adjust VrefHspeed
} CPU_VREF_OVERRIDE;
///===============================================================================
/// MEM_PARAMETER_STRUCT
/// This data structure is used to pass wrapper parameters to the memory configuration code
@ -2116,6 +2124,8 @@ typedef struct _MEM_PARAMETER_STRUCT {
///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE}
IN UINT16 CustomVddioSupport; ///< CustomVddioSupport
///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE}
IN CPU_VREF_OVERRIDE CpuVrefOverride[2][4]; ///< Structure to adjust VrefHspeed
///< PerDct, Per MemPstate
} MEM_PARAMETER_STRUCT;
@ -2858,6 +2868,7 @@ typedef struct {
IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control
IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround
IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround
IN BOOLEAN CfgFchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update
} FCH_PLATFORM_POLICY;
@ -2993,7 +3004,7 @@ typedef struct {
///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy
IN CONST FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy
IN BOOLEAN CfgIommuSupport; ///< IOMMU support
IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing
@ -3087,6 +3098,7 @@ typedef struct {
IN BOOLEAN CfgAcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING}
IN BOOLEAN CfgSmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING}
IN BOOLEAN CfgSmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR}
IN UINT16 CfgBootUpDisplayDevice; ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE}
IN BOOLEAN Reserved; ///< reserved...
} BUILD_OPT_CFG;
@ -3171,6 +3183,9 @@ typedef struct _PLATFORM_CONFIGURATION {
IN BOOLEAN AcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING}
IN BOOLEAN SmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING}
IN BOOLEAN SmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR}
IN UINT16 BootUpDisplayDevice; ///< The boot up display device selected.
///< If equal to 0 default setting in VBIOS for boot up display devices
///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE}
} PLATFORM_CONFIGURATION;
@ -3404,6 +3419,7 @@ typedef struct {
OUT UINT8 Channel:2; ///< Channel ID
OUT UINT8 Dimm:2; ///< DIMM ID
OUT UINT8 DimmPresent:1; ///< Dimm Present
OUT BOOLEAN Interleaved; ///< Interleaved;
OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
///< of memory mapped to the referenced Memory Device.
OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with

63
src/vendorcode/amd/pi/00670F00/AMD.h
View File

@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,12 +45,8 @@
#ifndef _AMD_H_
#define _AMD_H_
#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
#define AGESA_REVISION "Arch2008"
#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
#define AGESA_ID "AGESA"
//
//
@ -58,8 +54,11 @@
//
//
#define LAST_ENTRY 0xFFFFFFFFul
#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
/* coreboot binaryPI - start */
#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
/* coreboot binaryPI - end */
#define IOCF8 0xCF8
#define IOCFC 0xCFC
@ -130,37 +129,27 @@ typedef enum ACCESS_WIDTH {
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle
AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle
AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle
AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle
AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
FCH_INIT_RESET = 0x00040000,
FCH_INIT_ENV = 0x00041000,
FCH_INIT_MID = 0x00042000,
FCH_INIT_LATE = 0x00043000,
FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
FCH_INIT_S3_LATE_RESTORE = 0x00045000,
AMD_SET_VALUE_invalid = 0x00081000,
AMD_GET_VALUE_invalid = 0x00082000
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle
AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle
AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle
AMD_INIT_RTB ///< AmdInitRtb entry point handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */

4
src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h
View File

@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -656,7 +656,7 @@ typedef struct {
*/
typedef struct {
REGISTER_TABLE_TIME_POINT TimePoint; ///< Time point
CONST REGISTER_TABLE** TableList; ///< The table list.
CONST REGISTER_TABLE* CONST * CONST TableList; ///< The table list.
} REGISTER_TABLE_AT_GIVEN_TP;
/*------------------------------------------------------------------------------------------*/
/*

48
src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h
View File

@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -164,7 +164,7 @@ AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES);
*
*/
typedef AGESA_STATUS F_CPU_DISABLE_PSTATE (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -185,7 +185,7 @@ typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE;
*
*/
typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN BOOLEAN WaitForChange,
IN AMD_CONFIG_PARAMS *StdHeader
@ -210,7 +210,7 @@ typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE;
*
*/
typedef BOOLEAN F_CPU_GET_IDD_MAX (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
@ -231,7 +231,7 @@ typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX;
*
*/
typedef AGESA_STATUS F_CPU_GET_TSC_RATE (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES * FamilySpecificServices,
OUT UINT32 *FreqInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -252,7 +252,7 @@ typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE;
* @retval AGESA_SUCCESS FreqInMHz is valid.
*/
typedef AGESA_STATUS F_CPU_GET_NB_FREQ (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FreqInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -276,7 +276,7 @@ typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ;
* @retval AGESA_STATUS Northbridge frequency is valid
*/
typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
OUT UINT32 *MinFreqInMHz,
@ -306,7 +306,7 @@ typedef F_CPU_GET_MIN_MAX_NB_FREQ *PF_CPU_GET_MIN_MAX_NB_FREQ;
* @retval FALSE NbPstate is disabled or invalid
*/
typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
@ -333,7 +333,7 @@ typedef F_CPU_GET_NB_PSTATE_INFO *PF_CPU_GET_NB_PSTATE_INFO;
*
*/
typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbVidUpdateAll,
IN AMD_CONFIG_PARAMS *StdHeader
@ -358,7 +358,7 @@ typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED;
*
*/
typedef BOOLEAN F_CPU_GET_NB_IDD_MAX (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
OUT UINT32 *NbIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
@ -381,7 +381,7 @@ typedef F_CPU_GET_NB_IDD_MAX *PF_CPU_GET_NB_IDD_MAX;
* @retval FALSE The core was previously launched, or has a problem.
*/
typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 CoreNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -401,7 +401,7 @@ typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH;
* @return One-based number of physical cores on current processor
*/
typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -420,7 +420,7 @@ typedef F_CPU_NUMBER_OF_PHYSICAL_CORES *PF_CPU_NUMBER_OF_PHYSICAL_CORES;
* @return The AP's unique core number
*/
typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -449,7 +449,7 @@ typedef enum {
* @retval CoreIdPositionOne Core Id is low
*/
typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -468,7 +468,7 @@ typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_AP
*
*/
typedef VOID (F_CPU_SET_WARM_RESET_FLAG) (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
);
@ -488,7 +488,7 @@ typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG;
*
*/
typedef VOID (F_CPU_GET_WARM_RESET_FLAG) (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
);
@ -509,7 +509,7 @@ typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG;
*
*/
typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **FamilySpecificArray,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
@ -530,7 +530,7 @@ typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY;
*
*/
typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN OUT PLATFORM_FEATS *FeaturesUnion,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -552,7 +552,7 @@ typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC
* @retval FALSE The NB PState feature is not enabled.
*/
typedef BOOLEAN F_IS_NB_PSTATE_ENABLED (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -571,7 +571,7 @@ typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED;
*
*/
typedef REGISTER_TABLE_AT_GIVEN_TP *F_GET_REGISTER_TABLE_LIST (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
@ -590,7 +590,7 @@ typedef F_GET_REGISTER_TABLE_LIST *PF_GET_REGISTER_TABLE_LIST;
*
*/
typedef F_FAM_SPECIFIC_WORKAROUND **F_GET_WORKAROUND_TABLE (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,
OUT UINT16 *NumberOfWorkaroundTableEntries,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -614,7 +614,7 @@ typedef enum {
*
*/
typedef VOID F_PERFORM_EARLY_INIT_ON_CORE (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
@ -644,7 +644,7 @@ typedef struct _S_PERFORM_EARLY_INIT_ON_CORE {
*
*/
typedef VOID F_GET_EARLY_INIT_TABLE (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
@ -853,7 +853,7 @@ GetFeatureServicesFromLogicalId (
*/
VOID
GetEmptyArray (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **Empty,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader

4
src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
View File

@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -236,7 +236,7 @@ typedef struct {
/// Logical CPU ID Table
typedef struct {
IN UINT32 Elements; ///< Number of Elements
IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
IN CONST CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
} LOGICAL_ID_TABLE;
// MSRs

5
src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h
View File

@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -937,6 +937,7 @@ typedef struct {
UINT32 FchCpuId; ///< Saving CpuId for FCH Module.
BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
FCH_CS FchCsSupport; ///< FCH Cs function structure
BOOLEAN FchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update
} FCH_MISC;
@ -1405,7 +1406,7 @@ UINT8 USB30Gen1PreEmLe; ///< PTUSB30PCS_B3 genI pre-emphasis level
///PTUSBTxStructure
typedef struct {
PT_USB31Tx USB31Tx[2]; ///< USB31Tx setting
PT_USB30Tx USB30Tx[3]; ///< USB30Tx setting
PT_USB30Tx USB30Tx[6]; ///< USB30Tx setting
UINT8 USB20B2Tx00; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[0]
UINT8 USB20B2Tx05; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[5]
UINT8 USB20B3Tx1113; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[13][11]

3
src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h
View File

@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -81,6 +81,7 @@ BOOLEAN FchCheckST (IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader);
UINT64 FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchInitResetRequest (IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Fch Ab Routines

4
src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h
View File

@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -115,6 +115,6 @@
#include "FchBiosRamUsage.h"
#include "AmdFch.h"
extern BUILD_OPT_CFG UserOptions;
extern CONST BUILD_OPT_CFG UserOptions;
#endif // _FCH_PLATFORM_H_

15
src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h
View File

@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -87,6 +87,8 @@
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDS_DEBUG_PORT_SIZE_IN_BYTES
* IDS_DEBUG_TP_PREFIX
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
* IDSOPT_DEBUG_CODE_ENABLED
* IDSOPT_IDT_EXCEPTION_TRAP
@ -94,12 +96,10 @@
*
**/
//#include "Ids.h"
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#define IDS_MMAP_SERIAL_PORT
#ifdef DEBUG
#define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_CONTROL_ENABLED FALSE
@ -109,12 +109,17 @@
#undef IDS_DEBUG_PRINT_MASK
#endif
#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_ALL | GFX_MISC | CPU_TRACE_ALL | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
#ifdef IDS_MMAP_SERIAL_PORT
#define IDSOPT_SERIAL_PORT 0xfedc6000
#else
#define IDSOPT_SERIAL_PORT 0x3F8
#endif
#define IDSOPT_HEAP_CHECKING TRUE
#define IDSOPT_TRACE_BLD_CFG TRUE
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#define IDSOPT_DEBUG_CODE_ENABLED TRUE
#define IDSOPT_C_OPTIMIZATION_DISABLED TRUE
//#define IDSOPT_ASSERT_ENABLED TRUE
#else
#define IDSOPT_IDS_ENABLED FALSE
//#define IDSOPT_ERROR_TRAP_ENABLED FALSE