tegra124: fix the dangerous VPR write order
Currently we put the VPR write code just right before the AVP is going to freeze. We have no idea does the write operation successful or not before halting the AVP. And the power_on_main_cpu should be the last step of that. So we make a fix to change the order. BUG=none BRANCH=none TEST=LP0 suspend stress test and check the VPR is correct; LP0 suspend stress test with video playback Original-Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192029 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 51473811fa477cca9ad9cbafdaad4fd4a2309234) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia28329e38fcf12994594b73c805d061804aa01c4 Reviewed-on: http://review.coreboot.org/7459 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
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@ -583,13 +583,13 @@ void lp0_resume(void)
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config_tsc();
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config_tsc();
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power_on_main_cpu();
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// Disable VPR.
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// Disable VPR.
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write32(0, mc_video_protect_size_mb_ptr);
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write32(0, mc_video_protect_size_mb_ptr);
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write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
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write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
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mc_video_protect_reg_ctrl_ptr);
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mc_video_protect_reg_ctrl_ptr);
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power_on_main_cpu();
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// Halt the AVP.
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// Halt the AVP.
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while (1)
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while (1)
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write32(FLOW_MODE_STOP | EVENT_JTAG,
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write32(FLOW_MODE_STOP | EVENT_JTAG,
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