mb/ocp/deltalake: Add OCP Delta Lake mainboard
OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Jonathan Zhang
Patrick Georgi
parent
08ef4f10c7
commit
826523b679
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# type this to get working .config:
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# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.deltalake
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CONFIG_VENDOR_OCP=y
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CONFIG_BOARD_OCP_DELTALAKE=y
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CONFIG_HAVE_IFD_BIN=y
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CONFIG_HAVE_ME_BIN=y
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CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
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CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
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CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
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CONFIG_CPU_UCODE_BINARIES="site-local/deltalake/mbf5065a.mcb"
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CONFIG_ADD_FSP_BINARIES=y
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CONFIG_FSP_T_FILE="site-local/deltalake/Server_T.fd"
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CONFIG_FSP_M_FILE="site-local/deltalake/Server_M.fd"
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CONFIG_FSP_S_FILE="site-local/deltalake/Server_S.fd"
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CONFIG_ME_BIN_PATH="site-local/deltalake/flashregion_2_intel_me.bin"
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CONFIG_IFD_BIN_PATH="site-local/deltalake/flashregion_0_flashdescriptor.bin"
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@ -0,0 +1,32 @@
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if BOARD_OCP_DELTALAKE
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_65536
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select FSP_CAR
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select HAVE_ACPI_TABLES
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select MAINBOARD_USES_FSP2_0
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select SOC_INTEL_COOPERLAKE_SP
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select SUPERIO_ASPEED_AST2400
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config MAINBOARD_DIR
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string
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default "ocp/deltalake"
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config MAINBOARD_PART_NUMBER
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string
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default "DeltaLake"
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config MAINBOARD_FAMILY
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string
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default "DeltaLake"
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config MAX_SOCKET
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int
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default 1
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
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endif # BOARD_OCP_DELTALAKE
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config BOARD_OCP_DELTALAKE
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bool "DeltaLake"
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## SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
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CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
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CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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Name (_S0, Package () // mandatory system state
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{
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0x00, 0x00, 0x00, 0x00
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})
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Name (_S5, Package () // mandatory system state
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{
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0x07, 0x00, 0x00, 0x00
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})
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (DBG0, SystemIO, 0x80, 0x02)
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Field (DBG0, ByteAcc, Lock, Preserve)
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{
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IO80, 8,
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IO81, 8
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}
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/* IO-Trap at 0x800.
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* This is the ACPI->SMI communication interface.
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*/
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OperationRegion (IO_T, SystemIO, 0x800, 0x10)
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Field (IO_T, ByteAcc, NoLock, Preserve)
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{
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Offset (0x8),
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TRP0, 8 /* IO-Trap at 0x808 */
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}
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OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400)
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Field (PSYS, ByteAcc, NoLock, Preserve)
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{
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PLAT, 32, // Platform ID
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// IOAPIC
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APC0, 1, // PCH IOAPIC Enable
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AP00, 1, // PC00 IOAPIC Enable
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AP01, 1, // PC01 IOAPIC Enable
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AP02, 1, // PC02 IOAPIC Enable
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AP03, 1, // PC03 IOAPIC Enable
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AP04, 1, // PC04 IOAPIC Enable
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AP05, 1, // PC05 IOAPIC Enable
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AP06, 1, // PC06 IOAPIC Enable
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AP07, 1, // PC07 IOAPIC Enable
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AP08, 1, // PC08 IOAPIC Enable
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AP09, 1, // PC09 IOAPIC Enable
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AP10, 1, // PC10 IOAPIC Enable
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AP11, 1, // PC11 IOAPIC Enable
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AP12, 1, // PC12 IOAPIC Enable
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AP13, 1, // PC13 IOAPIC Enable
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AP14, 1, // PC14 IOAPIC Enable
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AP15, 1, // PC15 IOAPIC Enable
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AP16, 1, // PC16 IOAPIC Enable
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AP17, 1, // PC17 IOAPIC Enable
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AP18, 1, // PC18 IOAPIC Enable
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AP19, 1, // PC19 IOAPIC Enable
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AP20, 1, // PC20 IOAPIC Enable
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AP21, 1, // PC21 IOAPIC Enable
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AP22, 1, // PC22 IOAPIC Enable
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AP23, 1, // PC23 IOAPIC Enable
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RESA, 7,
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SKOV, 1, // Override Socket APIC Id
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RES0, 7,
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// Power Management
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TPME, 1,
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CSEN, 1,
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C3EN, 1,
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C6EN, 1,
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C7EN, 1,
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MWOS, 1,
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PSEN, 1,
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EMCA, 1,
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HWAL, 2,
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KPRS, 1,
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MPRS, 1,
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TSEN, 1,
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FGTS, 1,
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OSCX, 1,
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RESX, 1,
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// RAS
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CPHP, 8,
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IIOP, 8,
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IIOH, 64,
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PRBM, 32,
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P0ID, 32,
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P1ID, 32,
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P2ID, 32,
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P3ID, 32,
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P4ID, 32,
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P5ID, 32,
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P6ID, 32,
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P7ID, 32,
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P0BM, 64,
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P1BM, 64,
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P2BM, 64,
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P3BM, 64,
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P4BM, 64,
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P5BM, 64,
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P6BM, 64,
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P7BM, 64,
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MEBM, 16,
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MEBC, 16,
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CFMM, 32,
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TSSY, 32, // TODO: This is TSSZ in system booted from production FW
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M0BS, 64,
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M1BS, 64,
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M2BS, 64,
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M3BS, 64,
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M4BS, 64,
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M5BS, 64,
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M6BS, 64,
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M7BS, 64,
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M0RN, 64,
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M1RN, 64,
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M2RN, 64,
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M3RN, 64,
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M4RN, 64,
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M5RN, 64,
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M6RN, 64,
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M7RN, 64,
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SMI0, 32,
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SMI1, 32,
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SMI2, 32,
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SMI3, 32,
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SCI0, 32,
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SCI1, 32,
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SCI2, 32,
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SCI3, 32,
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MADD, 64,
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CUU0, 128,
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CUU1, 128,
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CUU2, 128,
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CUU3, 128,
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CUU4, 128,
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CUU5, 128,
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CUU6, 128,
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CUU7, 128,
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CPSP, 8,
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ME00, 128,
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ME01, 128,
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ME10, 128,
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ME11, 128,
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ME20, 128,
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ME21, 128,
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ME30, 128,
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ME31, 128,
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ME40, 128,
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ME41, 128,
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ME50, 128,
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ME51, 128,
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ME60, 128,
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ME61, 128,
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ME70, 128,
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ME71, 128,
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MESP, 16,
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LDIR, 64,
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PRID, 32,
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AHPE, 8,
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// VTD
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DHRD, 192,
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ATSR, 192,
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RHSA, 192,
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// SR-IOV
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WSIC, 8,
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WSIS, 16,
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WSIB, 8,
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WSID, 8,
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WSIF, 8,
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WSTS, 8,
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WHEA, 8,
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// BIOS Guard
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BGMA, 64,
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BGMS, 8,
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BGIO, 16,
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BGIL, 8,
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CNBS, 8,
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// USB3
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XHMD, 8,
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SBV1, 8,
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SBV2, 8,
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// HWPM
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HWEN, 2,
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ACEN, 1,
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HWPI, 1,
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RES1, 4,
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// IIO
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BB00, 8,
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BB01, 8,
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BB02, 8,
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BB03, 8,
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BB04, 8,
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BB05, 8,
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BB06, 8,
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BB07, 8,
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BB08, 8,
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BB09, 8,
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BB10, 8,
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BB11, 8,
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BB12, 8,
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BB13, 8,
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BB14, 8,
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BB15, 8,
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BB16, 8,
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BB17, 8,
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BB18, 8,
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BB19, 8,
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BB20, 8,
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BB21, 8,
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BB22, 8,
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BB23, 8,
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BB24, 8,
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BB25, 8,
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BB26, 8,
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BB27, 8,
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BB28, 8,
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BB29, 8,
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BB30, 8,
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BB31, 8,
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BB32, 8,
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BB33, 8,
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BB34, 8,
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BB35, 8,
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BB36, 8,
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BB37, 8,
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BB38, 8,
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BB39, 8,
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BB40, 8,
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BB41, 8,
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BB42, 8,
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BB43, 8,
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BB44, 8,
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BB45, 8,
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BB46, 8,
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BB47, 8,
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SGEN, 8,
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SG00, 8,
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SG01, 8,
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SG02, 8,
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SG03, 8,
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SG04, 8,
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SG05, 8,
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SG06, 8,
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SG07, 8,
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// Performance
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CLOD, 8,
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// XTU
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XTUB, 32,
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XTUS, 32,
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XMBA, 32,
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DDRF, 8,
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RT3S, 8,
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RTP0, 8,
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RTP3, 8,
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// FPGA
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FBB0, 8,
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FBB1, 8,
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FBB2, 8,
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FBB3, 8,
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FBB4, 8,
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FBB5, 8,
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FBB6, 8,
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FBB7, 8,
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FBL0, 8,
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FBL1, 8,
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FBL2, 8,
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FBL3, 8,
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FBL4, 8,
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FBL5, 8,
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FBL6, 8,
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FBL7, 8,
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P0FB, 8,
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P1FB, 8,
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P2FB, 8,
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P3FB, 8,
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P4FB, 8,
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P5FB, 8,
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P6FB, 8,
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P7FB, 8,
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FMB0, 32,
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FMB1, 32,
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FMB2, 32,
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FMB3, 32,
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FMB4, 32,
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FMB5, 32,
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FMB6, 32,
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FMB7, 32,
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FML0, 32,
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FML1, 32,
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FML2, 32,
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FML3, 32,
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FML4, 32,
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FML5, 32,
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FML6, 32,
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FML7, 32,
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FKPB, 32,
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FKB0, 8,
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FKB1, 8,
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FKB2, 8,
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FKB3, 8,
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FKB4, 8,
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FKB5, 8,
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FKB6, 8,
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FKB7, 8
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}
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/* SMI I/O Trap */
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Method (TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/*
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* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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Store (Arg0, PICM)
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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@ -0,0 +1,11 @@
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FLASH 64M {
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SI_ALL@0x0 0x3000000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x2FE7000
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PLATFORM_DATA@0x2FE8000 0x10000
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}
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SI_BIOS@0x3000000 0x1000000 {
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FMAP@0x0 0x800
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COREBOOT(CBFS)@0x800 0xfff800
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}
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}
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@ -0,0 +1,5 @@
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Board name: DeltaLake
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Category: server
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ROM protocol: SPI
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ROM socketed: yes
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Release year: 2020
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@ -0,0 +1,62 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#define ASPEED_SIO_PORT 0x2E
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static void enable_espi_lpc_io_windows(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For that end it is wired into BMC virtual port.
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*/
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uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
|
||||
uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
|
||||
|
||||
/* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
|
||||
pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
|
||||
/* LPC I/O enable: com1 and com2 */
|
||||
pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
|
||||
|
||||
/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
|
||||
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
|
||||
pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
|
||||
}
|
||||
|
||||
static uint8_t com_to_ast_sio(uint8_t com)
|
||||
{
|
||||
switch (com) {
|
||||
case 0:
|
||||
return AST2400_SUART1;
|
||||
case 1:
|
||||
return AST2400_SUART2;
|
||||
case 2:
|
||||
return AST2400_SUART3;
|
||||
case 4:
|
||||
return AST2400_SUART4;
|
||||
default:
|
||||
return AST2400_SUART1;
|
||||
}
|
||||
}
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
/* Open IO windows */
|
||||
enable_espi_lpc_io_windows();
|
||||
|
||||
/* Configure appropriate physical port of SuperIO chip off BMC */
|
||||
const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT,
|
||||
com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
|
||||
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
chip soc/intel/xeon_sp/cpx
|
||||
|
||||
register "pirqa_routing" = "PCH_IRQ11"
|
||||
register "pirqb_routing" = "PCH_IRQ10"
|
||||
register "pirqc_routing" = "PCH_IRQ11"
|
||||
register "pirqd_routing" = "PCH_IRQ11"
|
||||
register "pirqe_routing" = "PCH_IRQ11"
|
||||
register "pirqf_routing" = "PCH_IRQ11"
|
||||
register "pirqg_routing" = "PCH_IRQ11"
|
||||
register "pirqh_routing" = "PCH_IRQ11"
|
||||
|
||||
# configure device interrupt routing
|
||||
register "ir00_routing" = "0x3210" # IR00, Dev31
|
||||
register "ir01_routing" = "0x3210" # IR01, Dev30
|
||||
register "ir02_routing" = "0x3210" # IR02, Dev29
|
||||
register "ir03_routing" = "0x3210" # IR03, Dev28
|
||||
register "ir04_routing" = "0x3210" # IR04, Dev27
|
||||
|
||||
# configure interrupt polarity control
|
||||
register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
|
||||
register "ipc1" = "0x00000000" # IPC1
|
||||
register "ipc2" = "0x00000000" # IPC2
|
||||
register "ipc3" = "0x00000000" # IPC3
|
||||
|
||||
# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
|
||||
# FB production turbo_ratio_limit is 0x1f1f1f2022222325
|
||||
register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
|
||||
# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
|
||||
register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
|
||||
|
||||
# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
|
||||
register "pstate_req_ratio" = "0xa"
|
||||
|
||||
register "coherency_support" = "0"
|
||||
register "ats_support" = "0"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host bridge
|
||||
device pci 04.0 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.1 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.2 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.3 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.4 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.5 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.6 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 04.7 on end # Intel SkyLake-E CBDMA Registers
|
||||
device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers
|
||||
device pci 05.2 on end # Intel SkyLake-E RAS
|
||||
device pci 05.4 on end # Intel SkyLake-E IOAPIC
|
||||
device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers
|
||||
device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers
|
||||
device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers
|
||||
device pci 11.0 on end # Intel Device a26c: PCU
|
||||
|
||||
# PCH devices
|
||||
device pci 11.5 on end # Intel C620 Series Chipset Family SSATA Controller [AHCI mode]
|
||||
device pci 14.0 on end # Intel C620 Series Chipset Family USB 3.0 xHCI Controller
|
||||
|
||||
device pci 14.2 on end # Signal processing controller: Intel Device a231
|
||||
device pci 16.0 on end # Communication controller: Intel Device a23a
|
||||
device pci 16.1 on end # Communication controller: Intel Device a23b
|
||||
device pci 16.4 on end # Communication controller: Intel Device a23e
|
||||
device pci 1c.0 on end # PCI bridge: Intel Device a210
|
||||
device pci 1c.4 on end # PCI bridge: Intel Device a214
|
||||
device pci 1c.5 on end # PCI bridge: Intel Device a215
|
||||
device pci 1d.0 on end # PCI bridge: Intel Device a218
|
||||
device pci 1f.0 on end # ISA bridge: Intel Device a245
|
||||
device pci 1f.1 on end # p2sb
|
||||
device pci 1f.2 on end # Memory controller: Intel Device a221
|
||||
device pci 1f.3 on end # Audio device: Intel Device a270
|
||||
device pci 1f.4 on end # Intel C620 Series Chipset Family SMBus
|
||||
device pci 1f.5 on end # Intel C620 Series Chipset Family SPI Controller
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0 and up
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// platform ACPI tables
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/xeon_sp/cpx/acpi/globalnvs.asl>
|
||||
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
// CPX-SP ACPI tables
|
||||
#include <soc/intel/xeon_sp/cpx/acpi/uncore.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <soc/acpi.h>
|
||||
|
||||
void motherboard_fill_fadt(acpi_fadt_t *fadt)
|
||||
{
|
||||
fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSPS_UPD *params)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/api.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
/*
|
||||
* Configure GPIO depend on platform
|
||||
*/
|
||||
static void mainboard_config_gpios(FSPM_UPD *mupd)
|
||||
{
|
||||
/* To be implemented */
|
||||
}
|
||||
|
||||
static void mainboard_config_iio(FSPM_UPD *mupd)
|
||||
{
|
||||
/* To be implemented */
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
mainboard_config_gpios(mupd);
|
||||
mainboard_config_iio(mupd);
|
||||
}
|
||||
Loading…
Reference in New Issue