fixed the memory reset lines.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -1,6 +1,6 @@
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#define ASSEMBLY 1
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#define DEFAULT_CONSOLE_LOGLEVEL 8
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#define MAXIMUM_CONSOLE_LOGLEVEL 8
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#define DEFAULT_CONSOLE_LOGLEVEL 7
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#define MAXIMUM_CONSOLE_LOGLEVEL 7
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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@ -45,13 +45,13 @@ static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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}
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@ -60,7 +60,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
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udelay(90);
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}
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}
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@ -161,6 +161,7 @@ static void main(void)
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#endif
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};
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int needs_reset;
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print_emerg("H\n");
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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@ -180,6 +181,7 @@ static void main(void)
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print_info("ht reset -");
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soft_reset();
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}
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print_emerg("HER\n");
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#if 0
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print_pci_devices();
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#endif
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@ -197,8 +199,10 @@ static void main(void)
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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#if 0
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print_err("LET'S DO SOME MEMORY\n");
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#if 1
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/* Check the first 1M */
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ram_check(0x00000000, 0x000100000);
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#endif
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}
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