soc/intel/elkhartlake: Update IRQ routing settings
Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Tan, Lean Sheng
Werner Zeh
parent
e70344796a
commit
828e44c7c1
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@ -3,99 +3,161 @@
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#include <soc/irq.h>
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Name (PICP, Package () {
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Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ },
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/* D31 */
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Package () { 0x001FFFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x001FFFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x001FFFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x001FFFFF, 3, 0, PCH_IRQ_D },
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/* D30 */
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Package () { 0x001EFFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x001EFFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x001EFFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x001EFFFF, 3, 0, PCH_IRQ_D },
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/* Intel PSE Devices */
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Package () { 0x001DFFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x001DFFFF, 1, 0, PCH_IRQ34 },
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Package () { 0x001DFFFF, 2, 0, PCH_IRQ35 },
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Package () { 0x001DFFFF, 3, 0, PCH_IRQ36 },
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/* PCIe Root Ports */
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Package () { 0x001CFFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x001CFFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x001CFFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x001CFFFF, 3, 0, PCH_IRQ_D },
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/* Intel PSE I2C Devices */
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Package () { 0x001BFFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x001BFFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x001BFFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x001BFFFF, 3, 0, PCH_IRQ_D },
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/* D26 */
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Package () { 0x001AFFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x001AFFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x001AFFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x001AFFFF, 3, 0, PCH_IRQ_D },
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/* D25 */
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Package () { 0x0019FFFF, 0, 0, PCH_IRQ31 },
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Package () { 0x0019FFFF, 1, 0, PCH_IRQ32 },
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Package () { 0x0019FFFF, 2, 0, PCH_IRQ33 },
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/* Intel PSE Devices */
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Package () { 0x0018FFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x0018FFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x0018FFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x0018FFFF, 3, 0, PCH_IRQ_D },
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/* SATA */
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Package () { 0x0017FFFF, 0, 0, PCH_IRQ_A },
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/* ME Interfaces */
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Package () { 0x0016FFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x0016FFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x0016FFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x0016FFFF, 3, 0, PCH_IRQ_D },
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/* I2C Devices */
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Package () { 0x0015FFFF, 0, 0, PCH_IRQ27 },
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Package () { 0x0015FFFF, 1, 0, PCH_IRQ28 },
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Package () { 0x0015FFFF, 2, 0, PCH_IRQ29 },
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Package () { 0x0015FFFF, 3, 0, PCH_IRQ30 },
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/* USB Devices */
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Package () { 0x0014FFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x0014FFFF, 1, 0, PCH_IRQ_B },
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/* Intel PSE Devices */
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Package () { 0x0013FFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x0013FFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x0013FFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x0013FFFF, 3, 0, PCH_IRQ_D },
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/* D18 */
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Package () { 0x0012FFFF, 0, 0, PCH_IRQ24 },
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Package () { 0x0012FFFF, 1, 0, PCH_IRQ25 },
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Package () { 0x0012FFFF, 2, 0, PCH_IRQ26 },
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/* Intel PSE Devices */
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Package () { 0x0011FFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x0011FFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x0011FFFF, 2, 0, PCH_IRQ_C },
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Package () { 0x0011FFFF, 3, 0, PCH_IRQ_D },
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/* D16 */
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Package () { 0x0010FFFF, 0, 0, PCH_IRQ_A },
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Package () { 0x0010FFFF, 1, 0, PCH_IRQ_B },
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Package () { 0x0010FFFF, 2, 0, PCH_IRQ_C },
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/* SA GNA Device */
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Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 },
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/* SA IPU Device */
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Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 },
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Package () { 0x0008FFFF, 0, 0, PCH_IRQ_A },
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/* SA Thermal Device */
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Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 },
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Package () { 0x0004FFFF, 0, 0, PCH_IRQ_A },
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/* SA IGFX Device */
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Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 },
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Package () { 0x0002FFFF, 0, 0, PCH_IRQ_A },
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})
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Name (PICN, Package () {
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/* D31 */
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Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 },
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/* D30 */
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Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 },
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/* Intel PSE Devices */
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Package () { 0x001DFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001DFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001DFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001DFFFF, 3, 0, PCH_IRQ11 },
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/* PCIe Root Ports */
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Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 },
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/* Intel PSE I2C Devices */
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Package () { 0x001BFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001BFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001BFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001BFFFF, 3, 0, PCH_IRQ11 },
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/* D26 */
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Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001AFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001AFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001AFFFF, 3, 0, PCH_IRQ11 },
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/* D25 */
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Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 },
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/* Intel PSE Devices */
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Package () { 0x0018FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0018FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0018FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0018FFFF, 3, 0, PCH_IRQ11 },
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/* SATA */
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Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 },
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/* ME Interfaces */
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Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 },
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/* I2C Devices */
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Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 },
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/* USB Devices */
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Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 },
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/* Intel PSE Devices */
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Package () { 0x0013FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0013FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0013FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0013FFFF, 3, 0, PCH_IRQ11 },
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/* D18 */
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Package () { 0x0012FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0012FFFF, 2, 0, PCH_IRQ11 },
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/* Intel PSE Devices */
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Package () { 0x0011FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0011FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0011FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0011FFFF, 3, 0, PCH_IRQ11 },
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/* D16 */
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Package () { 0x0010FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0010FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0010FFFF, 2, 0, PCH_IRQ11 },
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/* SA GNA Device */
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Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 },
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/* SA IPU Device */
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Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 },
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/* SA IGFX Device */
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@ -8,29 +8,33 @@
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#define PCH_IRQ10 10
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#define PCH_IRQ11 11
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/* LPSS Device IRQs */
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#define LPSS_I2C0_IRQ 16
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#define LPSS_I2C1_IRQ 17
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#define LPSS_I2C2_IRQ 18
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#define LPSS_I2C3_IRQ 19
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#define LPSS_I2C4_IRQ 32
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#define LPSS_I2C5_IRQ 33
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#define LPSS_SPI0_IRQ 22
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#define LPSS_SPI1_IRQ 23
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#define LPSS_SPI2_IRQ 24
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#define LPSS_UART0_IRQ 20
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#define LPSS_UART1_IRQ 21
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#define LPSS_UART2_IRQ 34
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#define PCH_IRQ24 24
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#define PCH_IRQ25 25
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#define PCH_IRQ26 26
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#define PCH_IRQ27 27
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#define PCH_IRQ28 28
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#define PCH_IRQ29 29
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#define PCH_IRQ30 30
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#define PCH_IRQ31 31
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#define PCH_IRQ32 32
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#define PCH_IRQ33 33
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#define PCH_IRQ34 34
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#define PCH_IRQ35 35
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#define PCH_IRQ36 36
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/* PCI shared IRQs */
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#define PCH_IRQ_16 16
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#define PCH_IRQ_17 17
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#define PCH_IRQ_18 18
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#define PCH_IRQ_19 19
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#define PCH_IRQ_20 20
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#define PCH_IRQ_21 21
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#define PCH_IRQ_22 22
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#define PCH_IRQ_23 23
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#define PCH_IRQ_A 16
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#define PCH_IRQ_B 17
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#define PCH_IRQ_C 18
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#define PCH_IRQ_D 19
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#define PCH_IRQ_E 20
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#define PCH_IRQ_F 21
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#define PCH_IRQ_G 22
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#define PCH_IRQ_H 23
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/* LPSS Device IRQs */
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#define LPSS_UART0_IRQ 16
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#define LPSS_UART1_IRQ 17
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#define LPSS_UART2_IRQ 33
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#endif /* _EHL_IRQ_H_ */
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