From 8296fdd979023236a95c577a90f993250e0dcbb4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 10 Feb 2019 19:52:51 +0100 Subject: [PATCH] util/autoport: Separate NB and SB PCIe port IDs The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe root ports. Put the latter on sandybridge.go instead, and add missing IDs. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- util/autoport/bd82x6x.go | 11 +++++------ util/autoport/sandybridge.go | 8 ++++++++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 408d407e67..c4dcf0dd28 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -430,12 +430,11 @@ func init() { /* PCIe bridge */ for _, id := range []uint16{ - 0x0151, 0x0155, 0x1c10, 0x1c12, - 0x1c14, 0x1c16, 0x1c18, 0x1c1a, - 0x1c1c, 0x1c1e, 0x1e10, 0x1e12, - 0x1e14, 0x1e16, 0x1e18, 0x1e1a, - 0x1e1c, 0x1e1e, 0x1e25, 0x244e, - 0x2448, + 0x1c10, 0x1c12, 0x1c14, 0x1c16, + 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, + 0x1e10, 0x1e12, 0x1e14, 0x1e16, + 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, + 0x1e25, 0x244e, 0x2448, } { RegisterPCI(0x8086, id, GenericPCI{}) } diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 4c3bbe87b1..ff78809312 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -139,4 +139,12 @@ func init() { } { RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x0101, 0x0105, 0x0109, 0x010d, + 0x0151, 0x0155, 0x0159, 0x015d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } }