From 82aa8338c7485cf0139cc1a451e84d32194070fd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 7 Jan 2018 23:12:49 +0100 Subject: [PATCH] drivers/mrc_cache: Always generate an FMAP region This automatically generates an FMAP region for the MRC_CACHE driver which is easier to handle than a cbfsfile. Adds some spaces and more comments to Makefile.inc to improve readability. Tested on Thinkpad x200 with some proof of concept patches. Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/23150 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- Makefile.inc | 66 +++++++++++++++++++++++++++++- src/drivers/mrc_cache/Kconfig | 4 -- src/drivers/mrc_cache/Makefile.inc | 21 +--------- src/drivers/mrc_cache/mrc_cache.c | 19 +-------- util/cbfstool/default-x86.fmd | 1 + util/cbfstool/default.fmd | 1 + 6 files changed, 69 insertions(+), 43 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 2c25ab8910..4ce74745a9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -776,7 +776,11 @@ FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) # position and size of flashmap, relative to BIOS_BASE FMAP_FMAP_BASE := 0 -FMAP_FMAP_SIZE := 0x100 +FMAP_FMAP_SIZE := 0x200 + +# +# X86 CONSOLE FMAP region +# # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) @@ -787,8 +791,36 @@ FMAP_CONSOLE_BASE := 0 FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) + +# +# X86 RW_MRC_CACHE FMAP region +# +# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled +ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ + $(FMAP_CONSOLE_SIZE)), 0x10000) +else +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ + $(FMAP_FMAP_SIZE)), 0x10000) +endif +FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) +FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) +else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +FMAP_MRC_CACHE_BASE := 0 +FMAP_MRC_CACHE_SIZE := 0 +FMAP_MRC_CACHE_ENTRY := +endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) + +# +# X86 COREBOOT default cbfs FMAP region +# # position and size of CBFS, relative to BIOS_BASE +ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) +else FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE)) +endif FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd @@ -802,6 +834,10 @@ FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) # position and size of flashmap, relative to BIOS_BASE FMAP_FMAP_BASE := 0x20000 FMAP_FMAP_SIZE := 0x100 + +# +# NON-X86 CONSOLE FMAP region +# # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) @@ -812,8 +848,33 @@ FMAP_CONSOLE_BASE := 0 FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) + +# +# NON-X86 RW_MRC_CACHE FMAP region +# +# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled +ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ + $(FMAP_CONSOLE_SIZE)), 0x10000) +else +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ + $(FMAP_FMAP_SIZE)), 0x10000) +endif +FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) +FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) +else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +FMAP_MRC_CACHE_BASE := 0 +FMAP_MRC_CACHE_SIZE := 0 +FMAP_MRC_CACHE_ENTRY := +endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) + +# +# NON-X86 COREBOOT default cbfs FMAP region +# # position and size of CBFS, relative to BIOS_BASE -FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE) $(FMAP_CONSOLE_SIZE)) +FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE) $(FMAP_CONSOLE_SIZE) \ + $(FMAP_MRC_CACHE_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) endif # ifeq ($(CONFIG_ARCH_X86),y) @@ -825,6 +886,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ + -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index c367dcec95..543f310e66 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -5,10 +5,6 @@ config CACHE_MRC_SETTINGS if CACHE_MRC_SETTINGS -config MRC_SETTINGS_CACHE_BASE - hex - default 0xfffe0000 - config MRC_SETTINGS_CACHE_SIZE hex default 0x10000 diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc index 7c8732fb73..0d226fe89a 100644 --- a/src/drivers/mrc_cache/Makefile.inc +++ b/src/drivers/mrc_cache/Makefile.inc @@ -1,19 +1,2 @@ -ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) - -romstage-y += mrc_cache.c -ramstage-y += mrc_cache.c - -# Create and add the MRC cache to the cbfs image -ifneq ($(CONFIG_CHROMEOS),y) -$(obj)/mrc.cache: $(obj)/config.h - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_SETTINGS_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := $(CONFIG_MRC_SETTINGS_CACHE_BASE) -mrc.cache-type := mrc_cache -endif # ifneq ($(CONFIG_CHROMEOS),y) - -endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 9732185646..eec1591ce2 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -98,26 +98,9 @@ static const struct cache_region *cache_regions[] = { static int lookup_region_by_name(const char *name, struct region *r) { - /* This assumes memory mapped boot media just under 4GiB. */ - const uint32_t pointer_base_32bit = -CONFIG_ROM_SIZE; - if (fmap_locate_area(name, r) == 0) return 0; - - /* CHROMEOS builds must get their MRC cache from FMAP. */ - if (IS_ENABLED(CONFIG_CHROMEOS)) { - printk(BIOS_ERR, "MRC: Chrome OS lookup failure.\n"); - return -1; - } - - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) - return -1; - - /* Base is in the form of a pointer. Make it an offset. */ - r->offset = CONFIG_MRC_SETTINGS_CACHE_BASE - pointer_base_32bit; - r->size = CONFIG_MRC_SETTINGS_CACHE_SIZE; - - return 0; + return -1; } static const struct cache_region *lookup_region_type(int type) diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 1b6cfc8ba6..1f1aa4357b 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -11,6 +11,7 @@ FLASH@##ROM_BASE## ##ROM_SIZE## { BIOS@##BIOS_BASE## ##BIOS_SIZE## { FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## + ##MRC_CACHE_ENTRY## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } } diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd index 50b9bf0bd1..8f4819ebf9 100644 --- a/util/cbfstool/default.fmd +++ b/util/cbfstool/default.fmd @@ -14,6 +14,7 @@ FLASH@##ROM_BASE## ##ROM_SIZE## { BOOTBLOCK 128K FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## + ##MRC_CACHE_ENTRY## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } }