From 82b8c3d1b025af5076f769d7754b7e1ae6bf5950 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 15 Jan 2019 19:06:09 -0800 Subject: [PATCH] soc/intel/icelake: Fix AG3E programming in PMC According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped register but not pci configuration spaces, hence change the programming method in icelake pmc driver. Signed-off-by: Lijian Zhao Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7 Reviewed-on: https://review.coreboot.org/c/30947 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/icelake/pmc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 754aa5055d..9d1c47f63d 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -31,8 +31,9 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) { uint8_t reg8; + uint8_t *pmcbase = pmc_mmio_regs(); - reg8 = pci_read_config8(dev, GEN_PMCON_B); + reg8 = read8(pmcbase + GEN_PMCON_A); switch (s5pwr) { case MAINBOARD_POWER_STATE_OFF: @@ -46,7 +47,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) break; } - pci_write_config8(dev, GEN_PMCON_B, reg8); + write8(pmcbase + GEN_PMCON_A, reg8); } /*