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arch/x86: Drop some __SMM__ guards 

Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2019-11-05 19:06:56 +02:00 committed by Patrick Georgi
parent 44f1af2996
commit 82c0e7e3d5
24 changed files with 10 additions and 57 deletions
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3
src/cpu/intel/fsp_model_406dx/model_406dx.h
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@ -79,12 +79,9 @@
#define PSS_LATENCY_BUSMASTER 10
#ifndef __ROMCC__
#ifdef __SMM__
/* Lock MSRs */
void intel_model_406dx_finalize_smm(void);
#else
int cpu_config_tdp_levels(void);
#endif
#endif
#endif /* _CPU_INTEL_MODEL_406DX_H */

4
src/cpu/intel/model_2065x/model_2065x.h
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@ -69,14 +69,12 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
#ifdef __SMM__
/* Lock MSRs */
void intel_model_2065x_finalize_smm(void);
#else
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
#endif
/* Sanity check config options. */
#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)

4
src/cpu/intel/model_206ax/model_206ax.h
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@ -93,14 +93,12 @@
# error "CONFIG_IED_REGION_SIZE is not a power of 2"
#endif
#ifdef __SMM__
/* Lock MSRs */
void intel_model_206ax_finalize_smm(void);
#else
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
#endif
int get_platform_id(void);
#endif

2
src/include/cpu/x86/smm.h
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@ -86,7 +86,6 @@ struct smm_module_params {
/* smm_handler_t is called with arg of smm_module_params pointer. */
typedef asmlinkage void (*smm_handler_t)(void *);
#ifdef __SMM__
/* SMM Runtime helpers. */
/* Entry point for SMM modules. */
@ -95,7 +94,6 @@ asmlinkage void smm_handler_start(void *params);
/* Retrieve SMM save state for a given CPU. WARNING: This does not take into
* account CPUs which are configured to not save their state to RAM. */
void *smm_get_save_state(int cpu);
#endif /* __SMM__ */
/* SMM Module Loading API */

5
src/mainboard/google/stout/ec.h
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@ -22,10 +22,7 @@
#define EC_SMI_LID_CLOSED 0x2B
#ifndef __ACPI__
extern void stout_ec_init(void);
#endif
#ifdef __SMM__
void stout_ec_init(void);
void stout_ec_finalize_smm(void);
#endif

2
src/mainboard/hp/pavilion_m6_1035dx/ec.h
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@ -19,8 +19,6 @@
#include "mainboard.h"
#ifndef __SMM__
void pavilion_m6_1035dx_ec_init(void);
#endif
#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */

2
src/mainboard/lenovo/g505s/ec.h
View File

@ -19,8 +19,6 @@
#include "mainboard.h"
#ifndef __SMM__
void lenovo_g505s_ec_init(void);
#endif
#endif /* _MAINBOARD_LENOVO_G505S_EC_H */

2
src/mainboard/lenovo/s230u/ec.h
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@ -17,9 +17,7 @@
#ifndef _MAINBOARD_LENOVO_S230U_EC_H
#define _MAINBOARD_LENOVO_S230U_EC_H
#ifndef __SMM__
void lenovo_s230u_ec_init(void);
#endif
#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x)))
#define ec_mm_read(addr) (ECMM(0x100 + addr))

5
src/northbridge/intel/nehalem/nehalem.h
View File

@ -249,17 +249,14 @@ typedef struct {
#define PCI_DEVICE_ID_SB 0x0104
#define PCI_DEVICE_ID_IB 0x0154
#ifdef __SMM__
void intel_nehalem_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
void nehalem_early_initialization(int chipset_type);
void nehalem_late_initialization(void);
void mainboard_pre_raminit(void);
void mainboard_get_spd_map(u8 *spd_addrmap);
#endif /* !__SMM__ */
#endif
#endif
#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */

5
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -203,9 +203,8 @@ enum platform_type {
#ifndef __ASSEMBLER__
#ifdef __SMM__
void intel_sandybridge_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
void systemagent_early_init(void);
void sandybridge_init_iommu(void);
@ -213,8 +212,6 @@ void sandybridge_late_initialization(void);
void northbridge_romstage_finalize(int s3resume);
void early_init_dmi(void);
#endif /* !__SMM__ */
void pch_enable_lpc(void);
void mainboard_early_init(int s3resume);
void mainboard_config_superio(void);

2
src/soc/amd/picasso/include/soc/smi.h
View File

@ -232,8 +232,6 @@ void disable_gevent_smi(uint8_t gevent);
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
void soc_route_sci(uint8_t event);
#ifndef __SMM__
void enable_smi_generation(void);
#endif
#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */

2
src/soc/amd/stoneyridge/include/soc/smi.h
View File

@ -235,8 +235,6 @@ void disable_gevent_smi(uint8_t gevent);
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
void soc_route_sci(uint8_t event);
#ifndef __SMM__
void enable_smi_generation(void);
#endif
#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */

3
src/soc/intel/baytrail/include/soc/nvs.h
View File

@ -104,9 +104,8 @@ typedef struct global_nvs_t {
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
#endif /* _BAYTRAIL_NVS_H_ */

2
src/soc/intel/braswell/include/soc/nvs.h
View File

@ -107,9 +107,7 @@ typedef struct global_nvs_t {
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#if ENV_SMM
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
#endif /* _SOC_NVS_H_ */

3
src/soc/intel/broadwell/include/soc/nvs.h
View File

@ -96,9 +96,8 @@ typedef struct global_nvs_t {
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
#endif

2
src/soc/intel/broadwell/include/soc/xhci.h
View File

@ -50,8 +50,6 @@
#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
#ifdef __SMM__
void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
#endif
#endif

2
src/soc/intel/denverton_ns/include/soc/nvs.h
View File

@ -65,9 +65,7 @@ typedef struct global_nvs_t {
} __packed global_nvs_t;
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
#endif /* _DENVERTON_NS_NVS_H_ */

3
src/soc/intel/fsp_baytrail/include/soc/nvs.h
View File

@ -65,9 +65,8 @@ typedef struct {
} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
#endif /* _BAYTRAIL_NVS_H_ */

2
src/southbridge/amd/agesa/hudson/smi.h
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@ -71,8 +71,6 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
void hudson_disable_gevent_smi(uint8_t gevent);
void hudson_enable_acpi_cmd_smi(void);
#ifndef __SMM__
void hudson_enable_smi_generation(void);
#endif
#endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */

2
src/southbridge/amd/pi/hudson/smi.h
View File

@ -71,8 +71,6 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
void hudson_disable_gevent_smi(uint8_t gevent);
void hudson_enable_acpi_cmd_smi(void);
#ifndef __SMM__
void hudson_enable_smi_generation(void);
#endif
#endif /* _SOUTHBRIDGE_AMD_PI_HUDSON_SMI_H */

2
src/southbridge/intel/bd82x6x/nvs.h
View File

@ -155,8 +155,6 @@ typedef struct global_nvs_t {
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
void acpi_create_gnvs(global_nvs_t *gnvs);

3
src/southbridge/intel/fsp_rangeley/nvs.h
View File

@ -146,7 +146,6 @@ typedef struct {
} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif

3
src/southbridge/intel/ibexpeak/nvs.h
View File

@ -153,8 +153,7 @@ typedef struct global_nvs_t {
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
void acpi_create_gnvs(global_nvs_t *gnvs);

2
src/southbridge/intel/lynxpoint/nvs.h
View File

@ -130,9 +130,7 @@ typedef struct global_nvs_t {
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
void acpi_create_gnvs(global_nvs_t * gnvs);