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Remove all VIA CN700 boards 

Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I06840476ad187cbb6e6af554b5c8e8c4d66f6624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2018-05-24 00:04:22 +03:00
parent d840eb5719
commit 82d7609ea9
50 changed files with 0 additions and 1714 deletions
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30
src/mainboard/bcom/Kconfig
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@ -1,30 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if VENDOR_BCOM
choice
prompt "Mainboard model"
source "src/mainboard/bcom/*/Kconfig.name"
endchoice
source "src/mainboard/bcom/*/Kconfig"
config MAINBOARD_VENDOR
string
default "BCOM"
endif # VENDOR_BCOM

2
src/mainboard/bcom/Kconfig.name
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config VENDOR_BCOM
bool "BCOM"

25
src/mainboard/bcom/winnetp680/Kconfig
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@ -1,25 +0,0 @@
if BOARD_BCOM_WINNETP680
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_WINBOND_W83697HF
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default bcom/winnetp680
config MAINBOARD_PART_NUMBER
string
default "WinNET P680"
config IRQ_SLOT_COUNT
int
default 10
endif # BOARD_BCOM_WINNETP680

2
src/mainboard/bcom/winnetp680/Kconfig.name
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config BOARD_BCOM_WINNETP680
bool "WinNET P680"

1
src/mainboard/bcom/winnetp680/board_info.txt
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@ -1 +0,0 @@
Category: settop

28
src/mainboard/bcom/winnetp680/cmos.layout
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@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

64
src/mainboard/bcom/winnetp680/devicetree.cb
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@ -1,64 +0,0 @@
chip northbridge/via/cn700 # Northbridge
device domain 0 on # PCI domain
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control
device pci 0.3 on end # Memory Controller
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
chip southbridge/via/vt8237r # Southbridge
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
device pci f.0 on end # IDE
device pci 10.0 on end # UHCI
device pci 10.1 on end # UHCI
device pci 10.2 on end # UHCI
device pci 10.3 on end # UHCI
device pci 10.4 on end # EHCI
device pci 11.0 on # Southbridge LPC
chip superio/winbond/w83697hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.6 off end # Consumer IR
device pnp 2e.7 off end # Game port, GPIO 1
device pnp 2e.8 off end # MIDI port, GPIO 5
device pnp 2e.9 off end # GPIO 2-4
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HWM
io 0x60 = 0x290
end
end
end
device pci 11.5 on end # AC'97 audio
device pci 12.0 on end # Ethernet
end
end
device cpu_cluster 0 on # APIC cluster
chip cpu/via/c7 # VIA C7
device lapic 0 on end # APIC
end
end
end

50
src/mainboard/bcom/winnetp680/irq_tables.c
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@ -1,50 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x11 << 3) | 0x0, /* Interrupt router device */
0x828, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x3e, /* Checksum */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

94
src/mainboard/bcom/winnetp680/romstage.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <northbridge/via/cn700/raminit.h>
#include <cpu/x86/bist.h>
#include <delay.h>
#include <lib.h>
#include <spd.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83697hf/w83697hf.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void enable_mainboard_devices(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
/* bit = 0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
* 2 16.2 USB 3
* 1 16.4 USB EHCI
*/
pci_write_config8(dev, 0x50, 0x80);
/* bit = 1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
* 0 Internal Keyboard Controller
*/
pci_write_config8(dev, 0x51, 0x1d);
}
static const struct mem_controller ctrl = {
.d0f0 = 0x0000,
.d0f2 = 0x2000,
.d0f3 = 0x3000,
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { DIMM0 },
};
void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
winbond_set_clksel_48(SERIAL_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
}

27
src/mainboard/jetway/j7f2/Kconfig
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@ -1,27 +0,0 @@
if BOARD_JETWAY_J7F2 || BOARD_JETWAY_J7F4K1G2E || BOARD_JETWAY_J7F4K1G5D
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_FINTEK_F71805F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default jetway/j7f2
if BOARD_JETWAY_J7F2
config MAINBOARD_PART_NUMBER
string
default "J7f2"
endif # BOARD_JETWAY_J7F2
config IRQ_SLOT_COUNT
int
default 10
endif # BOARD_JETWAY_J7F2 || BOARD_JETWAY_J7F4K1G2E || BOARD_JETWAY_J7F4K1G5D

2
src/mainboard/jetway/j7f2/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_JETWAY_J7F2
bool "J7F2"

3
src/mainboard/jetway/j7f2/board_info.txt
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@ -1,3 +0,0 @@
Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F2
Category: mini
Release year: 2008

28
src/mainboard/jetway/j7f2/cmos.layout
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@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

62
src/mainboard/jetway/j7f2/devicetree.cb
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@ -1,62 +0,0 @@
chip northbridge/via/cn700 # Northbridge
device domain 0 on # PCI domain
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control
device pci 0.3 on end # Memory Controller
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
chip southbridge/via/vt8237r # Southbridge
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
device pci a.0 on end # Firewire
device pci f.0 on end # SATA
device pci f.1 on end # IDE
device pci 10.0 on end # OHCI
device pci 10.1 on end # OHCI
device pci 10.2 on end # OHCI
device pci 10.3 on end # OHCI
device pci 10.4 on end # EHCI
device pci 11.0 on # Southbridge LPC
chip superio/fintek/f71805f # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.b on # HWM
io 0x60 = 0xec00
end
end
end
device pci 11.5 on end # AC'97 audio
# device pci 11.6 off end # AC'97 Modem
device pci 12.0 on end # Ethernet
end
end
device cpu_cluster 0 on # APIC cluster
chip cpu/via/c7 # VIA C7
device lapic 0 on end # APIC
end
end
end

50
src/mainboard/jetway/j7f2/irq_tables.c
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@ -1,50 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x11 << 3) | 0x0, /* Interrupt router device */
0x828, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x3e, /* Checksum */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

98
src/mainboard/jetway/j7f2/romstage.c
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@ -1,98 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <northbridge/via/cn700/raminit.h>
#include <cpu/x86/bist.h>
#include <delay.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71805f/f71805f.h>
#include <lib.h>
#include <spd.h>
#if CONFIG_TTYS0_BASE == 0x2f8
#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
#else
#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
#endif
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void enable_mainboard_devices(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
/* bit=0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
* 2 16.2 USB 3
* 1 16.4 USB EHCI
*/
pci_write_config8(dev, 0x50, 0x80);
/* bit=1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
* 0 Internal Keyboard Controller
*/
pci_write_config8(dev, 0x51, 0x1d);
}
static const struct mem_controller ctrl = {
.d0f0 = 0x0000,
.d0f2 = 0x2000,
.d0f3 = 0x3000,
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { DIMM0 },
};
void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
}

8
src/mainboard/jetway/j7f4k1g2e/Kconfig
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@ -1,8 +0,0 @@
if BOARD_JETWAY_J7F4K1G2E
# Dummy for abuild
config MAINBOARD_PART_NUMBER
string
default "J7f4K1G2E"
endif

2
src/mainboard/jetway/j7f4k1g2e/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_JETWAY_J7F4K1G2E
bool "J7F4K1G2E"

4
src/mainboard/jetway/j7f4k1g2e/board_info.txt
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@ -1,4 +0,0 @@
Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E
Category: mini
Clone of: jetway/j7f2
Release year: 2009

8
src/mainboard/jetway/j7f4k1g5d/Kconfig
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@ -1,8 +0,0 @@
if BOARD_JETWAY_J7F4K1G5D
# Dummy for abuild
config MAINBOARD_PART_NUMBER
string
default "J7f4K1G5D"
endif

2
src/mainboard/jetway/j7f4k1g5d/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_JETWAY_J7F4K1G5D
bool "J7F4K1G5D"

4
src/mainboard/jetway/j7f4k1g5d/board_info.txt
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@ -1,4 +0,0 @@
Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G5D
Category: mini
Clone of: jetway/j7f2
Release year: 2008

25
src/mainboard/via/epia-cn/Kconfig
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@ -1,25 +0,0 @@
if BOARD_VIA_EPIA_CN
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_VIA_VT1211
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default via/epia-cn
config MAINBOARD_PART_NUMBER
string
default "EPIA-CN"
config IRQ_SLOT_COUNT
int
default 9
endif # BOARD_VIA_EPIA_CN

2
src/mainboard/via/epia-cn/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_VIA_EPIA_CN
bool "EPIA-CN"

4
src/mainboard/via/epia-cn/board_info.txt
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@ -1,4 +0,0 @@
Category: mini
Board name: EPIA-CN10000EG / EPIA-CN13000G
Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400
Release year: 2006

28
src/mainboard/via/epia-cn/cmos.layout
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@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

61
src/mainboard/via/epia-cn/devicetree.cb
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@ -1,61 +0,0 @@
chip northbridge/via/cn700 # Northbridge
device domain 0 on # PCI domain
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control
device pci 0.3 on end # Memory Controller
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
chip southbridge/via/vt8237r # Southbridge
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
device pci f.0 on end # IDE
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
device pci 10.0 on end # OHCI
device pci 10.1 on end # OHCI
device pci 10.2 on end # OHCI
device pci 10.3 on end # OHCI
device pci 10.4 on end # EHCI
device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
chip superio/via/vt1211 # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.b on # HWM
io 0x60 = 0xec00
end
end
end
device pci 11.5 on end # AC'97 audio
# device pci 11.6 off end # AC'97 Modem
device pci 12.0 on end # Ethernet
end
end
device cpu_cluster 0 on # APIC cluster
chip cpu/via/c7 # VIA C7
device lapic 0 on end # APIC
end
end
end

49
src/mainboard/via/epia-cn/irq_tables.c
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x11 << 3) | 0x0, /* Interrupt router device */
0xc20, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x66, /* Checksum */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x14 << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0d << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0e << 3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x13 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x11 << 3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x10 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x12 << 3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

86
src/mainboard/via/epia-cn/romstage.c
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@ -1,86 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <lib.h>
#include <northbridge/via/cn700/raminit.h>
#include <cpu/x86/bist.h>
#include <delay.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include "southbridge/via/vt8237r/early_serial.c"
#include <spd.h>
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void enable_mainboard_devices(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
/* bit = 0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
* 2 16.2 USB 3
* 1 16.4 USB EHCI
*/
pci_write_config8(dev, 0x50, 0x80);
/* bit = 1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
* 0 Internal Keyboard Controller
*/
pci_write_config8(dev, 0x51, 0x1d);
}
static const struct mem_controller ctrl = {
.d0f0 = 0x0000,
.d0f2 = 0x2000,
.d0f3 = 0x3000,
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { DIMM0 },
};
void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
enable_vt8237r_serial();
console_init();
enable_smbus();
smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
report_bist_failure(bist);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
}

35
src/mainboard/via/pc2500e/Kconfig
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@ -1,35 +0,0 @@
if BOARD_VIA_PC2500E
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_ITE_IT8716F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default via/pc2500e
config MAINBOARD_PART_NUMBER
string
default "pc2500e"
config IRQ_SLOT_COUNT
int
default 10
config VGA_BIOS_FILE
string
default "M14CRT.ROM"
config VGA_BIOS_ID
string
default "1106,3344"
endif # BOARD_VIA_PC2500E

2
src/mainboard/via/pc2500e/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_VIA_PC2500E
bool "pc2500e"

6
src/mainboard/via/pc2500e/board_info.txt
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@ -1,6 +0,0 @@
Category: mini
Board URL: http://www.idot.com.tw/en/products/mb-pc2500e/
ROM package: PLCC
ROM socketed: y
Flashrom support: y
Release year: 2007

43
src/mainboard/via/pc2500e/cmos.layout
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@ -1,43 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
entries
#start-bit length config config-ID name
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

89
src/mainboard/via/pc2500e/devicetree.cb
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@ -1,89 +0,0 @@
chip northbridge/via/cn700 # Northbridge
device domain 0 on # PCI domain
subsystemid 0x1019 0xaa51 inherit
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control
device pci 0.3 on end # Memory Controller
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
chip southbridge/via/vt8237r # Southbridge
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
device pci f.0 on end # SATA
device pci f.1 on end # IDE
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
device pci 10.0 on end # UHCI
device pci 10.1 on end # UHCI
device pci 10.2 on end # UHCI
device pci 10.3 on end # UHCI
device pci 10.4 on end # EHCI
device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
chip superio/ite/it8716f # Super I/O
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 off # COM2 (N/A on this board)
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.4 on # Environment controller
io 0x60 = 0x290
io 0x62 = 0x0000
irq 0x70 = 9
end
device pnp 2e.5 off # PS/2 keyboard (not used)
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 off # PS/2 mouse (not used)
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x0000
io 0x62 = 0x0800
io 0x64 = 0x0000
end
device pnp 2e.8 off # MIDI port (N/A)
io 0x60 = 0x300
irq 0x70 = 10
end
device pnp 2e.9 off # Game port (N/A)
io 0x60 = 0x201
end
device pnp 2e.a on # Consumer IR
io 0x60 = 0x310
irq 0x70 = 11
end
end
end
device pci 11.5 on end # AC'97 audio
# device pci 11.6 off end # AC'97 modem (N/A)
device pci 12.0 on end # Ethernet
end
end
device cpu_cluster 0 on # APIC cluster
chip cpu/via/c7 # VIA C7
device lapic 0 on end # APIC
end
end
end

49
src/mainboard/via/pc2500e/irq_tables.c
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x11 << 3) | 0x0, /* Interrupt router device */
0x828, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x3e, /* Checksum */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

95
src/mainboard/via/pc2500e/mptable.c
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@ -1,95 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
* Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
* (Thanks to LSRA University of Mannheim for their support)
* Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#include "southbridge/via/vt8237r/vt8237r.h"
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
/* Now, assemble the table. */
mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin))
// PCI slot 1
PCI_INT(0, 8, 0, 16);
PCI_INT(0, 8, 1, 17);
PCI_INT(0, 8, 2, 18);
PCI_INT(0, 8, 3, 19);
// PCI slot 2
PCI_INT(0, 9, 0, 17);
PCI_INT(0, 9, 1, 18);
PCI_INT(0, 9, 2, 19);
PCI_INT(0, 9, 3, 16);
// SATA
PCI_INT(0, 15, 1, 20);
// USB
PCI_INT(0, 16, 0, 21);
PCI_INT(0, 16, 1, 21);
PCI_INT(0, 16, 2, 21);
PCI_INT(0, 16, 3, 21);
// Audio
PCI_INT(0, 17, 2, 22);
// Ethernet
PCI_INT(0, 18, 0, 23);
/* Onboard VGA */
PCI_INT(1, 0, 0, 16);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, 0);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

61
src/mainboard/via/pc2500e/romstage.c
View File

@ -1,61 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <northbridge/via/cn700/raminit.h>
#include <cpu/x86/bist.h>
#include <delay.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static const struct mem_controller ctrl = {
.d0f0 = 0x0000,
.d0f2 = 0x2000,
.d0f3 = 0x3000,
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
};
void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
report_bist_failure(bist);
ddr_ram_setup(&ctrl);
}

32
src/mainboard/winnet/Kconfig
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@ -1,32 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if VENDOR_WINNET
choice
prompt "Mainboard model"
source "src/mainboard/winnet/*/Kconfig.name"
endchoice
source "src/mainboard/winnet/*/Kconfig"
config MAINBOARD_VENDOR
string
default "WinNET"
endif # VENDOR_WINNET

4
src/mainboard/winnet/Kconfig.name
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@ -1,4 +0,0 @@
config VENDOR_WINNET
bool "WinNET"
help
WinNET boards. Used in various thin client appliances.

47
src/mainboard/winnet/g170/Kconfig
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@ -1,47 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_WINNET_G170
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_WINBOND_W83697HF
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default winnet/g170
config MAINBOARD_PART_NUMBER
string
default "G170"
config IRQ_SLOT_COUNT
int
default 10
config PAYLOAD_CONFIGFILE
string
depends on PAYLOAD_SEABIOS
default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
endif # BOARD_WINNET_G170

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src/mainboard/winnet/g170/Kconfig.name
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@ -1,5 +0,0 @@
config BOARD_WINNET_G170
bool "WinNET G170 (Neoware CA19, IGEL 2110)"
help
G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.

51
src/mainboard/winnet/g170/acpi_tables.c
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/*
* This file is part of the coreboot project.
*
* Based on mainboard/via/epia-m700/acpi_tables.c
*
* Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
* Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include "southbridge/via/vt8237r/vt8237r.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Create all subtables for processors. */
current = acpi_create_madt_lapics(current);
/* Write SB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
VT8237R_APIC_ID, IO_APIC_ADDR, 0);
/* IRQ9 ACPI active low. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
/* IRQ0 -> APIC IRQ2. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0x0);
return current;
}

9
src/mainboard/winnet/g170/board_info.txt
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@ -1,9 +0,0 @@
Category: mini
Vendor name: WinNET
Board name: G170
ROM package: PLCC
ROM protocol: Parallel
ROM socketed: y
Flashrom support: y
Release year: 2006
Clone of: bcom/winnetp680

28
src/mainboard/winnet/g170/cmos.layout
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@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 8 e unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

3
src/mainboard/winnet/g170/config_seabios
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@ -1,3 +0,0 @@
# VT8237R won't DMA between 0xc0000 and 0x100000
# CONFIG_MALLOC_UPPERMEMORY is not set

64
src/mainboard/winnet/g170/devicetree.cb
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chip northbridge/via/cn700 # Northbridge
device domain 0 on # PCI domain
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control
device pci 0.3 on end # Memory Controller
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
chip southbridge/via/vt8237r # Southbridge
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
device pci f.0 on end # IDE
device pci 10.0 on end # UHCI
device pci 10.1 on end # UHCI
device pci 10.2 on end # UHCI
device pci 10.3 on end # UHCI
device pci 10.4 on end # EHCI
device pci 11.0 on # Southbridge LPC
chip superio/winbond/w83697hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.6 off end # Consumer IR
device pnp 2e.7 off end # Game port, GPIO 1
device pnp 2e.8 off end # MIDI port, GPIO 5
device pnp 2e.9 off end # GPIO 2-4
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HWM
io 0x60 = 0x290
end
end
end
device pci 11.5 on end # AC'97 audio
device pci 12.0 on end # Ethernet
end
end
device cpu_cluster 0 on # APIC cluster
chip cpu/via/c7 # VIA C7
device lapic 0 on end # APIC
end
end
end

43
src/mainboard/winnet/g170/dsdt.asl
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@ -1,43 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20170227 // OEM revision
)
{
/* Sleep states */
Name (\_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
Name (\_S5, Package (0x04) { 0x02, 0x02, 0x02, 0x02 })
/* Interrupt model */
Method (_PIC, 1) {
Store (Arg0, \_SB.PCI0.ISAC.APIC)
}
Scope (\_SB) {
/* PCI bus */
Device (PCI0) {
#include <northbridge/via/cn700/acpi/hostbridge.asl>
#include <southbridge/via/vt8237r/acpi/lpc.asl>
#include <southbridge/via/vt8237r/acpi/default_irq_route.asl>
}
}
}

50
src/mainboard/winnet/g170/irq_tables.c
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@ -1,50 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x11 << 3) | 0x0, /* Interrupt router device */
0x828, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x3e, /* Checksum */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

55
src/mainboard/winnet/g170/mainboard.c
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@ -1,55 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/acpi.h>
static void mainboard_final(void *chip_info)
{
/* A B C D */
static const unsigned char irq_map[4] = { 11, 5, 10, 0 };
struct device *lpc_dev;
printk(BIOS_INFO, "Setting up G170 IRQ routing...\n");
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
/* Disable APIC */
pci_write_config8(lpc_dev, 0x58, pci_read_config8(lpc_dev, 0x58) & ~0x40);
/* Share INTE-INTH with INTA-INTD */
pci_write_config8(lpc_dev, 0x46, 0x00);
/* Route INTA-INTD */
pci_write_config8(lpc_dev, 0x55, irq_map[0] << 4);
pci_write_config8(lpc_dev, 0x56, irq_map[1] << 4 | irq_map[2]);
pci_write_config8(lpc_dev, 0x57, irq_map[3]);
/* Assign IRQ numbers to known devices for non-PnP OSes */
pci_assign_irqs(0x00, 0x10, irq_map);
pci_assign_irqs(0x00, 0x11, irq_map);
pci_assign_irqs(0x00, 0x12, irq_map);
pci_assign_irqs(0x01, 0x00, irq_map);
}
struct chip_operations mainboard_ops = {
CHIP_NAME("WinNET G170")
.final = mainboard_final,
};

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src/mainboard/winnet/g170/romstage.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <northbridge/via/cn700/raminit.h>
#include <cpu/x86/bist.h>
#include <delay.h>
#include <lib.h>
#include <spd.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83697hf/w83697hf.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void enable_mainboard_devices(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
/* bit = 0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
* 2 16.2 USB 3
* 1 16.4 USB EHCI
*/
pci_write_config8(dev, 0x50, 0x80);
/* bit = 1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
* 0 Internal Keyboard Controller
*/
pci_write_config8(dev, 0x51, 0x1d);
}
static const struct mem_controller ctrl = {
.d0f0 = 0x0000,
.d0f2 = 0x2000,
.d0f3 = 0x3000,
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { DIMM0 },
};
void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
winbond_set_clksel_48(SERIAL_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
}