soc/intel/skylake: Refactor memory layout calculation
This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.
usable memory start = TOLUD - Generic memory size -
- soc specific reserve memory size.
Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
Aaron Durbin
parent
19dbffd010
commit
82ef364f9a
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@ -101,6 +101,126 @@ static bool is_ptt_enable(void)
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return false;
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}
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/* Calculate PTT size */
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static size_t get_ptt_size(void)
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{
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/* Allocate 4KB for PTT if enabled */
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return is_ptt_enable() ? 4*KiB : 0;
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}
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/* Calculate Trace Hub size */
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static size_t get_tracehub_size(uintptr_t dram_base,
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const struct soc_intel_skylake_config *config)
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{
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uintptr_t tracehub_base = dram_base;
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size_t tracehub_size = 0;
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if (!config->ProbelessTrace)
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return 0;
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/* GDXC MOT */
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tracehub_base -= GDXC_MOT_MEMORY_SIZE;
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/* Round down to natual boundary accroding to PSMI size */
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tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE);
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/* GDXC IOT */
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tracehub_base -= GDXC_IOT_MEMORY_SIZE;
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/* PSMI buffer area */
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tracehub_base -= PSMI_BUFFER_AREA_SIZE;
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/* Tracehub Area Size */
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tracehub_size = dram_base - tracehub_base;
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return tracehub_size;
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}
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/* Calculate PRMRR size based on user input PRMRR size and alignment */
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static size_t get_prmrr_size(uintptr_t dram_base,
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const struct soc_intel_skylake_config *config)
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{
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uintptr_t prmrr_base = dram_base;
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size_t prmrr_size;
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if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
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prmrr_size = 1*MiB;
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else
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prmrr_size = config->PrmrrSize;
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if (!prmrr_size)
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return 0;
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/*
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* PRMRR Sizes that are > 1MB and < 32MB are
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* not supported and will fail out.
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*/
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if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))
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die("PRMRR Sizes that are > 1MB and < 32MB are not"
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"supported!\n");
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prmrr_base -= prmrr_size;
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if (prmrr_size >= 32*MiB)
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prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);
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/* PRMRR Area Size */
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prmrr_size = dram_base - prmrr_base;
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return prmrr_size;
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}
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/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */
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static size_t calculate_traditional_mem_size(uintptr_t dram_base,
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const struct device *dev)
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{
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uintptr_t traditional_mem_base = dram_base;
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size_t traditional_mem_size;
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if (dev->enabled) {
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/* Read BDSM from Host Bridge */
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traditional_mem_base -= sa_get_dsm_size();
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/* Read BGSM from Host Bridge */
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traditional_mem_base -= sa_get_gsm_size();
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}
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/* Get TSEG size */
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traditional_mem_base -= sa_get_tseg_size();
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/* Get DPR size */
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if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
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traditional_mem_base -= sa_get_dpr_size();
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/* Traditional Area Size */
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traditional_mem_size = dram_base - traditional_mem_base;
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return traditional_mem_size;
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}
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/*
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* Calculate Intel Reserved Memory size based on
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* PRMRR size, Trace Hub config and PTT selection.
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*/
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static size_t calculate_reserved_mem_size(uintptr_t dram_base,
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const struct device *dev)
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{
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uintptr_t reserve_mem_base = dram_base;
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size_t reserve_mem_size;
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const struct soc_intel_skylake_config *config;
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config = dev->chip_info;
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/* Get PRMRR size */
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reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);
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/* Get Tracehub size */
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reserve_mem_base -= get_tracehub_size(reserve_mem_base, config);
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/* Get PTT size */
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reserve_mem_base -= get_ptt_size();
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/* Traditional Area Size */
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reserve_mem_size = dram_base - reserve_mem_base;
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return reserve_mem_size;
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}
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/*
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* Host Memory Map:
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*
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@ -133,75 +253,55 @@ static bool is_ptt_enable(void)
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* the base registers from each other to determine sizes of the regions. In
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* other words, the memory map is in a fixed order no matter what.
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*/
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static u32 calculate_dram_base(void)
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static uintptr_t calculate_dram_base(void)
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{
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const struct soc_intel_skylake_config *config;
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uintptr_t dram_base;
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const struct device *dev;
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uint32_t dram_base;
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uint32_t prmrr_base;
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size_t prmrr_size;
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dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
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if (!dev)
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die("ERROR - device not found!");
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die("ERROR - IGD device not found!");
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/* Read TOLUD from Host Bridge offset */
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dram_base = sa_get_tolud_base();
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if (dev->enabled) {
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/* Read BDSM from Host Bridge */
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dram_base -= sa_get_dsm_size();
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/* Get Intel Traditional Memory Range Size */
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dram_base -= calculate_traditional_mem_size(dram_base, dev);
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/* Read BGSM from Host Bridge */
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dram_base -= sa_get_gsm_size();
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}
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/* Get TSEG size */
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dram_base -= sa_get_tseg_size();
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/* Get DPR size */
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if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
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dram_base -= sa_get_dpr_size();
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config = dev->chip_info;
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if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
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prmrr_size = 1*MiB;
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else
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prmrr_size = config->PrmrrSize;
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if (prmrr_size > 0) {
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/*
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* PRMRR Sizes that are > 1MB and < 32MB are
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* not supported and will fail out.
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*/
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if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))
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die("PRMRR Sizes that are > 1MB and < 32MB are not"
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"supported!\n");
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prmrr_base = dram_base - prmrr_size;
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if (prmrr_size >= 32*MiB)
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prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);
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dram_base = prmrr_base;
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}
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if (config->ProbelessTrace) {
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/* GDXC MOT */
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dram_base -= GDXC_MOT_MEMORY_SIZE;
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/* Round down to natual boundary accroding to PSMI size */
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dram_base = ALIGN_DOWN(dram_base, PSMI_BUFFER_AREA_SIZE);
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/* GDXC IOT */
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dram_base -= GDXC_IOT_MEMORY_SIZE;
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/* PSMI buffer area */
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dram_base -= PSMI_BUFFER_AREA_SIZE;
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}
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if (is_ptt_enable())
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dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */
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/* Get Intel Reserved Memory Range Size */
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dram_base -= calculate_reserved_mem_size(dram_base, dev);
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return dram_base;
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}
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/* Get usable system memory start address */
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static u32 top_of_32bit_ram(void)
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/*
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* +-------------------------+ Top of RAM (aligned)
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* | System Management Mode |
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* | code and data | Length: CONFIG_TSEG_SIZE
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* | (TSEG) |
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* +-------------------------+ SMM base (aligned)
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* | |
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* | Chipset Reserved Memory |
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* | |
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* +-------------------------+ top_of_ram (aligned)
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* | |
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* | CBMEM Root |
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* | |
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* +-------------------------+
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* | |
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* | FSP Reserved Memory |
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* | |
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* +-------------------------+
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* | |
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* | Various CBMEM Entries |
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* | |
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* +-------------------------+ top_of_stack (8 byte aligned)
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* | |
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* | stack (CBMEM Entry) |
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* | |
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* +-------------------------+
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*/
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void *cbmem_top(void)
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{
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/*
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* Check if Tseg has been initialized, we will use this as a flag
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@ -210,39 +310,7 @@ static u32 top_of_32bit_ram(void)
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* PRMRR_MASK MSR lock bit is set.
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*/
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if (sa_get_tseg_base() == 0)
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return 0;
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return NULL;
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return calculate_dram_base();
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}
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void *cbmem_top(void)
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{
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/*
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* +-------------------------+ Top of RAM (aligned)
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* | System Management Mode |
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* | code and data | Length: CONFIG_TSEG_SIZE
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* | (TSEG) |
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* +-------------------------+ SMM base (aligned)
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* | |
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* | Chipset Reserved Memory |
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* | |
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* +-------------------------+ top_of_ram (aligned)
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* | |
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* | CBMEM Root |
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* | |
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* +-------------------------+
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* | |
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* | FSP Reserved Memory |
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* | |
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* +-------------------------+
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* | |
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* | Various CBMEM Entries |
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* | |
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* +-------------------------+ top_of_stack (8 byte aligned)
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* | |
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* | stack (CBMEM Entry) |
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* | |
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* +-------------------------+
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*/
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return (void *)top_of_32bit_ram();
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return (void *)calculate_dram_base();
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}
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