second round name simplification. drop the <component>_ prefix.

the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/include/cpu/amd/amdfam10_sysconf.h

@@ -20,7 +20,7 @@
 #ifndef AMDFAM10_SYSCONF_H
 #define AMDFAM10_SYSCONF_H
 
-#include "../../../northbridge/amd/amdfam10/amdfam10_nums.h"
+#include "northbridge/amd/amdfam10/nums.h"
 
 #include <cpu/x86/msr.h>
 

src/mainboard/a-trend/atc-6220/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

src/mainboard/a-trend/atc-6240/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)

src/mainboard/abit/be6-ii_v2_0/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 /* FIXME: It's a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 /* FIXME: It's a Winbond W83977EF, actually. */

src/mainboard/advantech/pcm-5820/romstage.c

@@ -26,7 +26,7 @@
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83977f/w83977f_early_serial.c"
+#include "superio/winbond/w83977f/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)

src/mainboard/amd/db800/romstage.c

@@ -33,7 +33,7 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

src/mainboard/amd/dbm690t/acpi_tables.c

@@ -26,7 +26,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
 

src/mainboard/amd/dbm690t/romstage.c

@@ -37,7 +37,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <spd.h>
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/amd/mahogany/acpi_tables.c

@@ -26,7 +26,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
 

src/mainboard/amd/mahogany/romstage.c

@@ -38,7 +38,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -61,7 +61,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/amd/pistachio/acpi_tables.c

@@ -26,7 +26,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
 

src/mainboard/amd/pistachio/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <usbdebug.h>
 #include <spd.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/amd/rumba/romstage.c

@@ -4,7 +4,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>

src/mainboard/amd/serengeti_cheetah/acpi_tables.c

@@ -17,7 +17,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include "mb_sysconf.h"
 
 #define DUMP_ACPI_TABLES 0

src/mainboard/amd/serengeti_cheetah/dsdt.asl

@@ -206,7 +206,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
         Z00A,   8
     }
 
-    #include "northbridge/amd/amdk8/amdk8_util.asl"
+    #include "northbridge/amd/amdk8/util.asl"
 
 }
 

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -24,7 +24,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -45,7 +45,7 @@
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -82,7 +82,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -60,7 +60,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/arima/hdama/romstage.c

@@ -16,7 +16,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
+#include "superio/nsc/pc87360/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/asi/mb_5blgp/romstage.c

@@ -26,7 +26,7 @@
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
-#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#include "superio/nsc/pc87351/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)

src/mainboard/asi/mb_5blmp/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#include "superio/nsc/pc87351/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/cs5530/enable_rom.c"
 

src/mainboard/asrock/939a785gmh/acpi_tables.c

@@ -26,7 +26,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
 

src/mainboard/asrock/939a785gmh/dsdt.asl

@@ -28,7 +28,7 @@ DefinitionBlock (
 	)
 {	/* Start of ASL file */
 	/* #include "acpi/debug.asl" */		/* Include global debug methods if needed */
-	#include "northbridge/amd/amdk8/amdk8_util.asl"
+	#include "northbridge/amd/amdk8/util.asl"
 
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 

src/mainboard/asrock/939a785gmh/romstage.c

@@ -39,7 +39,7 @@
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+#include "superio/winbond/w83627dhg/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/asus/a8n_e/romstage.c

@@ -34,7 +34,7 @@
 #include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/asus/a8v-e_se/romstage.c

@@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/asus/m2v-mx_se/acpi_tables.c

@@ -32,7 +32,7 @@
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
 #include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <cpu/amd/model_fxx_powernow.h>
 
 extern const unsigned char AmlCode[];

src/mainboard/asus/m2v-mx_se/dsdt.asl

@@ -24,7 +24,7 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 {
-	 #include "northbridge/amd/amdk8/amdk8_util.asl"
+	 #include "northbridge/amd/amdk8/util.asl"
 
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -44,7 +44,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/asus/m2v/acpi_tables.c

@@ -33,7 +33,7 @@
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
 #include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <cpu/amd/model_fxx_powernow.h>
 
 extern const unsigned char AmlCode[];

src/mainboard/asus/m2v/romstage.c

@@ -44,7 +44,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/asus/m4a78-em/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -60,7 +60,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/asus/m4a785-m/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -60,7 +60,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/asus/mew-am/romstage.c

@@ -29,7 +29,7 @@
 #include "northbridge/intel/i82810/raminit.h"
 #include "pc80/udelay_io.c"
 #include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

src/mainboard/asus/mew-vm/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
+#include "superio/smsc/lpc47b272/early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
 #include "cpu/x86/bist.h"
 #include "southbridge/intel/i82801ax/i82801ax.h"

src/mainboard/asus/p2b-d/romstage.c

@@ -32,7 +32,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

src/mainboard/asus/p2b-ds/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

src/mainboard/asus/p2b-f/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */

src/mainboard/asus/p2b-ls/romstage.c

@@ -33,7 +33,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

src/mainboard/asus/p2b/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

src/mainboard/asus/p3b-f/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */

src/mainboard/axus/tc320/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/cs5530/enable_rom.c"
 

src/mainboard/azza/pt-6ibd/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 /* FIXME: It's a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 /* FIXME: It's a Winbond W83977EF, actually. */

src/mainboard/bcom/winnet100/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/cs5530/enable_rom.c"
 

src/mainboard/bcom/winnetp680/romstage.c

@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
 static inline int spd_read_byte(unsigned device, unsigned address)

src/mainboard/biostar/m6tba/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)

src/mainboard/broadcom/blast/romstage.c

@@ -16,7 +16,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/nsc/pc87417/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/compaq/deskpro_en_sff_p600/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 /* FIXME: This should be PC97307 (but it's buggy at the moment)! */
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
 #include <lib.h>
 
 /* FIXME: This should be PC97307 (but it's buggy at the moment)! */

src/mainboard/dell/s1850/romstage.c

@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
-#include "superio/nsc/pc8374/pc8374_early_init.c"
+#include "superio/nsc/pc8374/early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "debug.c"

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -13,7 +13,7 @@
 #include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -14,7 +14,7 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

src/mainboard/eaglelion/5bcm/romstage.c

@@ -6,7 +6,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/cs5530/enable_rom.c"
 #include "northbridge/amd/gx1/raminit.c"

src/mainboard/ecs/p6iwp-fe/romstage.c

@@ -30,7 +30,7 @@
 #include "northbridge/intel/i82810/raminit.h"
 #include "pc80/udelay_io.c"
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <lib.h>
 
 void main(unsigned long bist)

src/mainboard/gigabyte/ga-6bxc/romstage.c

@@ -32,7 +32,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include "superio/ite/it8671f/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)

src/mainboard/gigabyte/ga-6bxe/romstage.c

@@ -33,7 +33,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
 static void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include "superio/ite/it8671f/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -46,8 +46,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8716f/it8716f_early_serial.c"
+#include "superio/ite/it8716f/early_serial.c"
-#include "superio/ite/it8716f/it8716f_early_init.c"
+#include "superio/ite/it8716f/early_init.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -64,7 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"

src/mainboard/gigabyte/m57sli/acpi_tables.c

@@ -29,7 +29,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <cpu/amd/model_fxx_powernow.h>
 #include <device/pci.h>
 #include <cpu/amd/amdk8_sysconf.h>

src/mainboard/gigabyte/m57sli/dsdt.asl

@@ -25,7 +25,7 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 {
-	#include "northbridge/amd/amdk8/amdk8_util.asl"
+	#include "northbridge/amd/amdk8/util.asl"
 
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on

src/mainboard/gigabyte/m57sli/romstage.c

@@ -42,8 +42,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8716f/it8716f_early_serial.c"
+#include "superio/ite/it8716f/early_serial.c"
-#include "superio/ite/it8716f/it8716f_early_init.c"
+#include "superio/ite/it8716f/early_init.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -71,7 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -38,7 +38,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -56,7 +56,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -60,7 +60,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/hp/dl145_g1/romstage.c

@@ -16,7 +16,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/hp/dl145_g3/romstage.c

@@ -46,9 +46,9 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/serverengines/pilot/pilot_early_serial.c"
+#include "superio/serverengines/pilot/early_serial.c"
-#include "superio/serverengines/pilot/pilot_early_init.c"
+#include "superio/serverengines/pilot/early_init.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/nsc/pc87417/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -74,7 +74,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	 return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -48,9 +48,9 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/serverengines/pilot/pilot_early_serial.c"
+#include "superio/serverengines/pilot/early_serial.c"
-#include "superio/serverengines/pilot/pilot_early_init.c"
+#include "superio/serverengines/pilot/early_init.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/nsc/pc87417/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -78,7 +78,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"

src/mainboard/hp/e_vectra_p2706t/romstage.c

@@ -27,7 +27,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 /* TODO: It's a PC87364 actually! */
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
+#include "superio/nsc/pc87360/early_serial.c"
 /* TODO: It's i810E actually! */
 #include "northbridge/intel/i82810/raminit.h"
 #include "cpu/x86/bist.h"

src/mainboard/ibase/mb899/romstage.c

@@ -32,7 +32,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/x86/bist.h>
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"

src/mainboard/ibm/e325/romstage.c

@@ -17,7 +17,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87366/pc87366_early_serial.c"
+#include "superio/nsc/pc87366/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/ibm/e326/romstage.c

@@ -17,7 +17,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87366/pc87366_early_serial.c"
+#include "superio/nsc/pc87366/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/iei/juki-511p/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "superio/winbond/w83977f/w83977f_early_serial.c"
+#include "superio/winbond/w83977f/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/fintek/f71859/f71859_early_serial.c"
+#include "superio/fintek/f71859/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -62,7 +62,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/iei/nova4899r/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -33,7 +33,7 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

src/mainboard/intel/d810e2cb/romstage.c

@@ -29,7 +29,7 @@
 #include "northbridge/intel/i82810/raminit.h"
 #include "pc80/udelay_io.c"
 #include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
 #include "gpio.c"
 #include <lib.h>
 

src/mainboard/intel/d945gclf/romstage.c

@@ -32,7 +32,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/x86/bist.h>
-#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
+#include "superio/smsc/lpc47m15x/early_serial.c"
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"

src/mainboard/intel/eagleheights/romstage.c

@@ -34,8 +34,8 @@
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "reset.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
 #include "northbridge/intel/i3100/i3100.h"
 #include "southbridge/intel/i3100/i3100.h"
 

src/mainboard/intel/jarrell/romstage.c

@@ -15,7 +15,7 @@
 #include "reset.c"
 #include "power_reset_check.c"
 #include "jarrell_fixups.c"
-#include "superio/nsc/pc87427/pc87427_early_init.c"
+#include "superio/nsc/pc87427/early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>

src/mainboard/intel/mtarvon/romstage.c

@@ -32,7 +32,7 @@
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>

src/mainboard/intel/truxton/romstage.c

@@ -34,7 +34,7 @@
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 

src/mainboard/intel/xe7501devkit/romstage.c

@@ -12,7 +12,7 @@
 #include "northbridge/intel/e7501/raminit.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/e7501/debug.c"
-#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
+#include "superio/smsc/lpc47b272/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>

src/mainboard/iwill/dk8_htx/acpi_tables.c

@@ -17,7 +17,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include "mb_sysconf.h"
 
 #define DUMP_ACPI_TABLES 0

src/mainboard/iwill/dk8_htx/dsdt.asl

@@ -206,7 +206,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
         Z00A,   8
     }
 
-    #include "northbridge/amd/amdk8/amdk8_util.asl"
+    #include "northbridge/amd/amdk8/util.asl"
 
 }
 

src/mainboard/iwill/dk8_htx/romstage.c

@@ -22,7 +22,7 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 

src/mainboard/iwill/dk8s2/romstage.c

@@ -22,7 +22,7 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 

src/mainboard/iwill/dk8x/romstage.c

@@ -22,7 +22,7 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 

src/mainboard/jetway/j7f24/romstage.c

@@ -32,7 +32,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/fintek/f71805f/f71805f_early_serial.c"
+#include "superio/fintek/f71805f/early_serial.c"
 #include <lib.h>
 #include <spd.h>
 

src/mainboard/jetway/pa78vm5/romstage.c

@@ -43,7 +43,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/fintek/f71863fg/f71863fg_early_serial.c"
+#include "superio/fintek/f71863fg/early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
@@ -67,7 +67,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"

src/mainboard/kontron/986lcd-m/romstage.c

@@ -33,7 +33,7 @@
 #include "option_table.h"
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
+#include "superio/winbond/w83627thg/early_serial.c"
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"

src/mainboard/kontron/kt690/acpi_tables.c

@@ -26,7 +26,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
 

src/mainboard/kontron/kt690/romstage.c

@@ -40,7 +40,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+#include "superio/winbond/w83627dhg/early_serial.c"
 #include <usbdebug.h>
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"

src/mainboard/lanner/em8510/romstage.c

@@ -36,7 +36,7 @@
 #include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
+#include "superio/winbond/w83627thg/early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 

src/mainboard/lippert/frontrunner/romstage.c

@@ -5,7 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -36,7 +36,7 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 
 /* Bit0 enables Spread Spectrum. */
 #define SMC_CONFIG	0x01

src/mainboard/lippert/literunner-lx/romstage.c

@@ -36,7 +36,7 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
 #if CONFIG_ONBOARD_IDE_SLAVE

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -36,7 +36,7 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 
 #define ManualConf 1		/* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000049C	/* Manual settings for the PLL */

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -36,7 +36,7 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
 #if CONFIG_ONBOARD_IDE_SLAVE

src/mainboard/mitac/6513wu/romstage.c

@@ -30,7 +30,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)

src/mainboard/msi/ms6119/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

src/mainboard/msi/ms6147/romstage.c

@@ -31,7 +31,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <cpu/x86/bist.h>
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)