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soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

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USBSUSPGQDIS is a disqualifier bit which will allow platform
to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this
bit will ensure that USB2 PHY SUS is power gated before entering s0ix.

BUG=b:175767084
BRANCH=dedede
TEST=s0ix works on drawcia and USB wake from s0ix works fine.

Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
This commit is contained in:
Krishna Prasad Bhat 2020-12-30 14:01:40 +05:30 committed by Karthik Ramasubramanian
parent 7ae375d3bc
commit 830306cc84
2 changed files with 16 additions and 0 deletions
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13
src/soc/intel/jasperlake/finalize.c
View file

@ -40,6 +40,8 @@ static void pch_handle_sideband(config_t *config)
static void pch_finalize(void)
{
uint32_t reg32;
uint8_t *pmcbase;
config_t *config;
/* TCO Lock down */
@ -62,6 +64,17 @@ static void pch_finalize(void)
if (config->PmTimerDisabled)
pmc_disable_acpi_timer();
pmcbase = pmc_mmio_regs();
if (config->s0ix_enable) {
/*
* Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated
* before entering s0ix.
*/
reg32 = read32(pmcbase + CPPMVRIC3);
reg32 &= ~USBSUSPGQDIS;
write32(pmcbase + CPPMVRIC3, reg32);
}
pch_handle_sideband(config);
pmc_clear_pmcon_sts();

3
src/soc/intel/jasperlake/include/soc/pmc.h
View file

@ -122,6 +122,9 @@
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)
#define CPPMVRIC3 0x1E4C
#define USBSUSPGQDIS (1 << 15)
#define IRQ_REG ACTL
#define SCI_IRQ_ADJUST 0
#define ACTL 0x1BD8