soc/amd/common/espi,mb/: Allow configuring open drain ALERT#

Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.

BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/amd/bilby/devicetree.cb

@@ -120,7 +120,7 @@ chip soc/amd/picasso
 		.io_mode = ESPI_IO_MODE_SINGLE,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 0,
 		.vw_ch_en = 0,
 		.oob_ch_en = 0,

src/mainboard/amd/majolica/devicetree.cb

@@ -7,7 +7,7 @@ chip soc/amd/cezanne
 		.io_mode = ESPI_IO_MODE_QUAD,
 		.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 1,
 		.vw_ch_en = 1,
 		.oob_ch_en = 1,

src/mainboard/amd/mandolin/variants/cereme/devicetree.cb

@@ -120,7 +120,7 @@ chip soc/amd/picasso
 		.io_mode = ESPI_IO_MODE_SINGLE,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 0,
 		.vw_ch_en = 0,
 		.oob_ch_en = 0,

src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb

@@ -120,7 +120,7 @@ chip soc/amd/picasso
 		.io_mode = ESPI_IO_MODE_SINGLE,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 0,
 		.vw_ch_en = 0,
 		.oob_ch_en = 0,

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -35,7 +35,7 @@ chip soc/amd/cezanne
 		.io_mode = ESPI_IO_MODE_QUAD,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 1,
 		.vw_ch_en = 1,
 		.oob_ch_en = 0,

src/mainboard/google/mancomb/variants/baseboard/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/amd/cezanne
 		.io_mode = ESPI_IO_MODE_QUAD,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 1,
 		.vw_ch_en = 1,
 		.oob_ch_en = 0,

src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb

@@ -230,7 +230,7 @@ chip soc/amd/picasso
 		.io_mode = ESPI_IO_MODE_QUAD,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 1,
 		.vw_ch_en = 1,
 		.oob_ch_en = 0,

src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb

@@ -223,7 +223,7 @@ chip soc/amd/picasso
 		.io_mode = ESPI_IO_MODE_QUAD,
 		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 		.crc_check_enable = 1,
-		.dedicated_alert_pin = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 		.periph_ch_en = 1,
 		.vw_ch_en = 1,
 		.oob_ch_en = 0,

src/soc/amd/common/block/include/amdblocks/espi.h

@@ -73,6 +73,12 @@ enum espi_op_freq {
 	ESPI_OP_FREQ_66_MHZ = ESPI_OP_FREQ_VALUE(2),
 };
 
+enum espi_alert_pin {
+	ESPI_ALERT_PIN_IN_BAND,
+	ESPI_ALERT_PIN_PUSH_PULL,
+	ESPI_ALERT_PIN_OPEN_DRAIN,
+};
+
 struct espi_config {
 	/* Bitmap for standard IO decodes. Use ESPI_DECODE_IO_* above. */
 	uint32_t std_io_decode_bitmap;
@@ -85,9 +91,9 @@ struct espi_config {
 	/* Slave configuration parameters */
 	enum espi_io_mode io_mode;
 	enum espi_op_freq op_freq_mhz;
+	enum espi_alert_pin alert_pin;
 
 	uint32_t crc_check_enable:1;
-	uint32_t dedicated_alert_pin:1;
 	uint32_t periph_ch_en:1;
 	uint32_t vw_ch_en:1;
 	uint32_t oob_ch_en:1;

src/soc/amd/common/block/lpc/espi_util.c

@@ -683,6 +683,29 @@ static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave
 	}
 }
 
+static void espi_set_alert_pin_config(enum espi_alert_pin alert_pin, uint32_t slave_caps,
+				    uint32_t *slave_config, uint32_t *ctrlr_config)
+{
+	switch (alert_pin) {
+	case ESPI_ALERT_PIN_IN_BAND:
+		*slave_config |= ESPI_SLAVE_ALERT_MODE_IO1;
+		return;
+	case ESPI_ALERT_PIN_PUSH_PULL:
+		*slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_PUSH_PULL_ALERT_SEL;
+		*ctrlr_config |= ESPI_ALERT_MODE;
+		return;
+	case ESPI_ALERT_PIN_OPEN_DRAIN:
+		if (!(slave_caps & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP))
+			die("eSPI peripheral does not support open drain alert!");
+
+		*slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL;
+		*ctrlr_config |= ESPI_ALERT_MODE;
+		return;
+	default:
+		die("Unknown espi alert config: %u!\n", alert_pin);
+	}
+}
+
 static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps)
 {
 	uint32_t slave_config = 0;
@@ -693,11 +716,7 @@ static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint
 		ctrlr_config |= ESPI_CRC_CHECKING_EN;
 	}
 
-	if (mb_cfg->dedicated_alert_pin) {
+	espi_set_alert_pin_config(mb_cfg->alert_pin, slave_caps, &slave_config, &ctrlr_config);
-		slave_config |= ESPI_SLAVE_ALERT_MODE_PIN;
-		ctrlr_config |= ESPI_ALERT_MODE;
-	}
-
 	espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config);
 	espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config);