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nb/intel/i945: Use ESMRAMC instead of 0x9e

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Macro renamed to be in accordance with the name used in the datasheet.

Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Elyes HAOUAS 2018-01-19 12:52:25 +01:00 committed by Martin Roth
parent 36e809ffd6
commit 8324d87bf4
3 changed files with 3 additions and 3 deletions
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2
src/northbridge/intel/i945/i945.h
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@ -75,7 +75,7 @@
#define LAC 0x97 /* Legacy Access Control */
#define TOLUD 0x9c /* Top of Low Used Memory */
#define SMRAM 0x9d /* System Management RAM Control */
#define ESMRAM 0x9e /* Extended System Management RAM Control */
#define ESMRAMC 0x9e /* Extended System Management RAM Control */
#define TOM 0xa0

2
src/northbridge/intel/i945/northbridge.c
View file

@ -95,7 +95,7 @@ static void pci_domain_set_resources(device_t dev)
uma_memory_size = uma_size * 1024ULL;
}
reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), ESMRAMC);
if (reg8 & 1) {
int tseg_size = 0;
printk(BIOS_DEBUG, "TSEG decoded, subtracting ");

2
src/northbridge/intel/i945/ram_calc.c
View file

@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void)
tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
/* if TSEG enabled subtract size */
switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC) & 0x07) {
case 0x01:
/* 1MB TSEG */
tom -= 0x100000;