mb/google/sarien: Enable DPTF
Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie
Duncan Laurie
parent
bfb001d1a0
commit
833a3a879d
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@ -64,4 +64,15 @@ DefinitionBlock(
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#include <ec/google/wilco/acpi/ec.asl>
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}
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#endif
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/cannonlake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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@ -30,6 +30,7 @@ chip soc/intel/cannonlake
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register "speed_shift_enable" = "1"
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register "s0ix_enable" = "1"
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register "dptf_enable" = "1"
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# Intel Common SoC Config
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
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@ -0,0 +1,59 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 100
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#define DPTF_TSR0_SENSOR_ID 1
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#define DPTF_TSR0_SENSOR_NAME "Thermal 1"
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#define DPTF_TSR0_PASSIVE 55
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#define DPTF_TSR0_CRITICAL 80
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#define DPTF_TSR1_SENSOR_ID 2
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#define DPTF_TSR1_SENSOR_NAME "Thermal 2"
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#define DPTF_TSR1_PASSIVE 55
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#define DPTF_TSR1_CRITICAL 80
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#undef DPTF_ENABLE_FAN_CONTROL
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#undef DPTF_ENABLE_CHARGER
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
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/* CPU Effect on Board */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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3000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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100 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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15000, /* PowerLimitMinimum */
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44000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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100 /* StepSize */
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}
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})
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@ -28,4 +28,7 @@
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/* Enable PS/2 keyboard */
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#define SIO_EC_ENABLE_PS2K
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/* Enable DPTF */
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#define EC_ENABLE_DPTF
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#endif
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@ -30,6 +30,7 @@ chip soc/intel/cannonlake
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register "speed_shift_enable" = "1"
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register "s0ix_enable" = "1"
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register "dptf_enable" = "1"
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# Intel Common SoC Config
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
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@ -0,0 +1,59 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 100
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#define DPTF_TSR0_SENSOR_ID 1
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#define DPTF_TSR0_SENSOR_NAME "Thermal 1"
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#define DPTF_TSR0_PASSIVE 55
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#define DPTF_TSR0_CRITICAL 80
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#define DPTF_TSR1_SENSOR_ID 2
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#define DPTF_TSR1_SENSOR_NAME "Thermal 2"
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#define DPTF_TSR1_PASSIVE 55
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#define DPTF_TSR1_CRITICAL 80
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#undef DPTF_ENABLE_FAN_CONTROL
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#undef DPTF_ENABLE_CHARGER
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
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/* CPU Effect on Board */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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3000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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100 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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15000, /* PowerLimitMinimum */
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44000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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100 /* StepSize */
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}
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})
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@ -28,4 +28,7 @@
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/* Enable PS/2 keyboard */
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#define SIO_EC_ENABLE_PS2K
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/* Enable DPTF */
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#define EC_ENABLE_DPTF
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#endif
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