hp/abm: Add new mainboard
The hp/abm board is used in network/server applications. Notes: - The hp/abm board is headless and therefore does not define CONFIG_GFXUMA, and does not require a video bios. - The micro USB connector on the board edge is connected to COM4 (i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3. - If you are using SeaBIOS it would also need to be configured to use the UART at I/O=2E8h. - This board has been tested with headless installed versions of Ubuntu 12.10 and Fedora 19. Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6116 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This commit is contained in:
Dave Frodin
Kyösti Mälkki
parent
e75deb69cc
commit
83405a1241
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@ -3,6 +3,8 @@ if VENDOR_HP
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choice
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prompt "Mainboard model"
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config BOARD_HP_ABM
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bool "ABM"
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config BOARD_HP_DL145_G1
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bool "ProLiant DL145 G1"
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config BOARD_HP_DL145_G3
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@ -17,6 +19,7 @@ config BOARD_HP_PAVILION_M6_1035DX
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endchoice
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source "src/mainboard/hp/abm/Kconfig"
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source "src/mainboard/hp/dl145_g1/Kconfig"
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source "src/mainboard/hp/dl145_g3/Kconfig"
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source "src/mainboard/hp/dl165_g6_fam10/Kconfig"
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,7 +18,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/azalia.h>
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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@ -47,257 +47,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/**
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* CODEC Initialization Table for Azalia HD Audio using Realtek ALC662 chip
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*/
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static const CODEC_ENTRY Alc662_VerbTbl[] =
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{
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{ 0x14, /*01014010*/ /* Port D - green headphone jack */
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(AZALIA_PINCFG_PORT_JACK << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
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| (AZALIA_PINCFG_DEVICE_LINEOUT << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_GREEN << 12)
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| (1 << 4)
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| (0 << 0)
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},
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{ 0x15, /*0x90170120*/ /* Port A - white speaker header */
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(AZALIA_PINCFG_PORT_FIXED << 30)
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| (AZALIA_PINCFG_LOCATION_INTERNAL << 24)
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| (AZALIA_PINCFG_DEVICE_SPEAKER << 20)
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| (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16)
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| (AZALIA_PINCFG_COLOR_WHITE << 12)
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| (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8)
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| (2 << 4)
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| (0 << 0)
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},
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{ 0x16, 0x411111F0 }, /* Port G - not connected */
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{ 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */
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(AZALIA_PINCFG_PORT_JACK << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
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| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_PINK << 12)
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| (4 << 4)
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| (0 << 0)
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},
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{ 0x19, /*0x02A19050*/ /* Port F - front panel header mic */
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(AZALIA_PINCFG_PORT_NC << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
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| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_PINK << 12)
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| (5 << 4)
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| (0 << 0)
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},
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{ 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */
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(AZALIA_PINCFG_PORT_NC << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
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| (AZALIA_PINCFG_DEVICE_LINEIN << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_BLUE << 12)
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| (4 << 4)
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| (0xF << 0)
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},
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{ 0x1B, /*0x02214030*/ /* Port E - front panel line-out */
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(AZALIA_PINCFG_PORT_NC << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
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| (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_GREEN << 12)
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| (3 << 4)
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| (0 << 0)
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},
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{ 0x1C, 0x411111F0 }, /* CD-in - Not Connected */
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{ 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */
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{ 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */
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{ 0xFF, 0xFFFFFFFF },
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};
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static const CODEC_TBL_LIST CodecTableList[] =
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{
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{0x10ec0662, (CODEC_ENTRY*)Alc662_VerbTbl},
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{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
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};
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#define FAN_INPUT_INTERNAL_DIODE 0
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#define FAN_INPUT_TEMP0 1
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#define FAN_INPUT_TEMP1 2
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#define FAN_INPUT_TEMP2 3
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#define FAN_INPUT_TEMP3 4
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#define FAN_INPUT_TEMP0_FILTER 5
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#define FAN_INPUT_ZERO 6
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#define FAN_INPUT_DISABLED 7
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#define FAN_AUTOMODE (1 << 0)
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#define FAN_LINEARMODE (1 << 1)
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#define FAN_STEPMODE ~(1 << 1)
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#define FAN_POLARITY_HIGH (1 << 2)
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#define FAN_POLARITY_LOW ~(1 << 2)
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/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
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#define FREQ_28KHZ 0x0
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#define FREQ_25KHZ 0x1
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#define FREQ_23KHZ 0x2
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#define FREQ_21KHZ 0x3
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#define FREQ_29KHZ 0x4
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#define FREQ_18KHZ 0x5
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#define FREQ_100HZ 0xF7
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#define FREQ_87HZ 0xF8
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#define FREQ_58HZ 0xF9
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#define FREQ_44HZ 0xFA
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#define FREQ_35HZ 0xFB
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#define FREQ_29HZ 0xFC
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#define FREQ_22HZ 0xFD
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#define FREQ_14HZ 0xFE
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#define FREQ_11HZ 0xFF
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/* imb_a180 Hardware Monitor Fan Control
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* Hardware limitation:
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* HWM failed to read the input temperture vi I2C,
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* if other software switch the I2C switch by mistake or intention.
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* We recommend to using IMC to control Fans, instead of HWM.
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*/
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#if 0
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static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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{
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FCH_HWM_FAN_CTR oem_factl[5] = {
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/* temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
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/* imb_a180 FanOUT0 Fan header J32 */
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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/* imb_a180 FanOUT1 Fan header J31*/
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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};
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LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
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/* Enable IMC fan control. the recommand way */
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#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1)
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/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
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FchParams->Hwm.HwMonitorEnable = TRUE;
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FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
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FchParams->Imc.ImcEnable = TRUE;
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FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
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FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
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LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
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/* Thermal Zone Parameter */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
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/* IMC Fan Policy temperature thresholds */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
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/* IMC Fan Policy PWM Settings */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
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/* IMC Function */
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FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8;
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/* NOTE:
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* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
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* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
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* so we remove it from AGESA code. Please Seee FchInitLateHwm.
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*/
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#else /* HWM fan control, the way not recommand */
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FchParams->Imc.ImcEnable = FALSE;
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FchParams->Hwm.HwMonitorEnable = TRUE;
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FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
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#endif /* CONFIG_HUDSON_IMC_FWM */
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}
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#endif
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/**
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* Fch Oem setting callback
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*
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@ -318,12 +67,9 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList;
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/* Azalia Controller Front Panel OEM Table Pointer */
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||||
|
||||
/* Fan Control */
|
||||
//oem_fan_control(FchParams_env);
|
||||
|
||||
/* XHCI configuration */
|
||||
FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
# Copyright (C) 2012-2014 Advanced Micro Devices, Inc.
|
||||
# Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -17,29 +18,27 @@
|
|||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
if BOARD_ASROCK_IMB_A180
|
||||
if BOARD_HP_ABM
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_AGESA_FAMILY16_KB
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
select SUPERIO_WINBOND_W83627UHG
|
||||
select SUPERIO_NUVOTON_NCT5104D
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asrock/imb-a180
|
||||
default hp/abm
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "IMB-A180"
|
||||
default "ABM"
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
|
|
@ -57,20 +56,8 @@ config IRQ_SLOT_COUNT
|
|||
int
|
||||
default 11
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config HUDSON_LEGACY_FREE
|
||||
bool
|
||||
default y
|
||||
default n
|
||||
|
||||
# bit 1,0 - pin 0
|
||||
# bit 3,2 - pin 1
|
||||
# bit 5,4 - pin 2
|
||||
# bit 7,6 - pin 3
|
||||
config AZ_PIN
|
||||
hex
|
||||
default 0x2
|
||||
|
||||
endif # BOARD_ASROCK_IMB_A180
|
||||
endif # BOARD_HP_ABM
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -14,7 +15,7 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -64,4 +65,4 @@
|
|||
//#define IDSOPT_HOST_HDT FALSE
|
||||
//#define IDS_DEBUG_PORT 0x80
|
||||
|
||||
#endif
|
||||
#endif /* _OPTION_IDS_H_ */
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -88,16 +89,10 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
|
|||
},
|
||||
/* DP1 to FCH */
|
||||
{
|
||||
0,
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to HDMI1/DP */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -35,7 +35,4 @@ Name(PMOD, One) /* Assume APIC */
|
|||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, }
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ Name(UOM9, 6)
|
|||
|
||||
/* USB Overcurrent GPEs */
|
||||
|
||||
#if 0 /* TODO: Update for imba180 */
|
||||
#if 0 /* TODO: Update */
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
Category: mini
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -76,7 +77,7 @@
|
|||
#define BLDOPT_REMOVE_SRAT FALSE //TRUE
|
||||
#define BLDOPT_REMOVE_SLIT FALSE //TRUE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE //TRUE
|
||||
#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_CDIT TRUE
|
||||
#define BLDOPT_REMOVE_DMI TRUE
|
||||
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
|
||||
|
|
@ -153,7 +154,7 @@
|
|||
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
|
||||
#define BLDCFG_1GB_ALIGN FALSE
|
||||
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
|
||||
#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
|
||||
#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE
|
||||
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
|
||||
#define BLDCFG_IOMMU_SUPPORT FALSE
|
||||
#define OPTION_GFX_INIT_SVIEW FALSE
|
||||
|
|
@ -344,11 +345,20 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
|
|||
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
|
||||
//#define BLDCFG_IR_PIN_CONTROL 0x33
|
||||
|
||||
GPIO_CONTROL imba180_gpio[] = {
|
||||
{183, Function1, GpioIn | GpioOutEnB | PullUpB},
|
||||
GPIO_CONTROL hp_abm_gpio[] = {
|
||||
{ 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED
|
||||
{ 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID
|
||||
{ 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH
|
||||
{ 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT
|
||||
{ 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L
|
||||
{ 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC
|
||||
{ 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L
|
||||
{ 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT
|
||||
{ 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT
|
||||
{ 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R
|
||||
{-1}
|
||||
};
|
||||
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
|
||||
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0])
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
|
|
@ -441,11 +451,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
|||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS (LAYERS_4),
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
|
||||
MOTHER_BOARD_LAYERS (LAYERS_6),
|
||||
|
||||
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2013 Advanced Micro Devices, Inc.
|
||||
# Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -28,76 +29,55 @@ chip northbridge/amd/agesa/family16kb/root_complex
|
|||
chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
|
||||
|
||||
chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # mPCIe slot
|
||||
device pci 2.3 on end # Realtek NIC
|
||||
device pci 2.4 on end # Edge Connector
|
||||
device pci 2.5 on end # Edge Connector
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 off end # unused
|
||||
device pci 2.2 on end # GPP0: NIC
|
||||
device pci 2.3 on end # GPP1: NIC
|
||||
device pci 2.4 off end # GPP2: unused
|
||||
device pci 2.5 off end # GPP3: unused
|
||||
end #chip northbridge/amd/agesa/family16kb
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on
|
||||
chip superio/winbond/w83627uhg
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 off end # LPT1
|
||||
device pnp 2e.2 on # COM1
|
||||
device pci 14.2 off end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/nuvoton/nct5104d
|
||||
device pnp 4e.0 off end # FDC
|
||||
device pnp 4e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2
|
||||
device pnp 4e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # KEYBRD
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 on # COM3
|
||||
io 0x60 = 0x3e8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.9 off end # GPIO
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b off end # HWMON
|
||||
device pnp 2e.c off end # PECI
|
||||
device pnp 2e.d on # COM4
|
||||
device pnp 4e.7 off end # GPIO
|
||||
device pnp 4e.8 off end # GPIO/WDT
|
||||
device pnp 4e.f off end # GPIO
|
||||
device pnp 4e.10 off end # COM3 used by port 80
|
||||
device pnp 4e.11 on # COM4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.e on # COM5
|
||||
io 0x60 = 0x3e0
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.f on # COM6
|
||||
io 0x60 = 0x2e0
|
||||
irq 0x70 = 3
|
||||
end
|
||||
end # w83627uhg
|
||||
end # LPC 0x439d
|
||||
device pci 14.7 on end # SD
|
||||
device pnp 4e.14 off end # PORT80
|
||||
register "irq_trigger_type" = "0" # 0 edge, 1 level
|
||||
end # nct5104d
|
||||
end #LPC
|
||||
device pci 14.7 off end # SD
|
||||
device pci 16.0 on end # USB
|
||||
device pci 16.2 on end # USB
|
||||
end #chip southbridge/amd/hudson
|
||||
|
||||
device pci 18.0 on end
|
||||
|
|
@ -108,10 +88,8 @@ chip northbridge/amd/agesa/family16kb/root_complex
|
|||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family16kb/root_complex
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -21,16 +22,97 @@
|
|||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <northbridge/amd/agesa/BiosCallOuts.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include <southbridge/amd/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/pci_devs.h>
|
||||
#include <northbridge/amd/agesa/family16kb/pci_devs.h>
|
||||
|
||||
void set_pcie_reset(void);
|
||||
void set_pcie_dereset(void);
|
||||
|
||||
/***********************************************************
|
||||
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
|
||||
* This table is responsible for physically routing the PIC and
|
||||
* IOAPIC IRQs to the different PCI devices on the system. It
|
||||
* is read and written via registers 0xC00/0xC01 as an
|
||||
* Index/Data pair. These values are chipset and mainboard
|
||||
* dependent and should be updated accordingly.
|
||||
*
|
||||
* These values are used by the PCI configuration space,
|
||||
* MP Tables. TODO: Make ACPI use these values too.
|
||||
*/
|
||||
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
|
||||
[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */
|
||||
[0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */
|
||||
[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */
|
||||
[0x40] = 0x0B,0x0B, /* IDE, SATA */
|
||||
};
|
||||
|
||||
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */
|
||||
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */
|
||||
[0x40] = 0x11,0x13, /* IDE, SATA */
|
||||
};
|
||||
|
||||
/*
|
||||
* This table defines the index into the picr/intr_data
|
||||
* tables for each device. Any enabled device and slot
|
||||
* that uses hardware interrupts should have an entry
|
||||
* in this table to define its index into the FCH
|
||||
* PCI_INTR register 0xC00/0xC01. This index will define
|
||||
* the interrupt that it should use. Putting PIRQ_A into
|
||||
* the PIN A index for a device will tell that device to
|
||||
* use PIC IRQ 10 if it uses PIN A for its hardware INT.
|
||||
*/
|
||||
static const struct pirq_struct mainboard_pirq_data[] = {
|
||||
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
|
||||
{GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
|
||||
{NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.2 */
|
||||
{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.3 */
|
||||
{NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.4 */
|
||||
{NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.5 */
|
||||
{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
|
||||
{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
|
||||
{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
|
||||
{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
|
||||
{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
|
||||
{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
|
||||
{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
|
||||
{SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCIB: 14.4 */
|
||||
{SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
|
||||
{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
|
||||
{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
pirq_data_ptr = mainboard_pirq_data;
|
||||
pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/* TODO: mainboard specific SB AGESA callback */
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* TODO: mainboard specific SB AGESA callback */
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
* Enable the dedicated functions of the board.
|
||||
**********************************************/
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
|
|
@ -38,6 +120,9 @@ static void mainboard_enable(device_t dev)
|
|||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -14,7 +15,7 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
|
@ -31,29 +32,21 @@
|
|||
#include <console/loglevel.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "cpu/x86/lapic.h"
|
||||
#include "southbridge/amd/agesa/hudson/hudson.h"
|
||||
#include "cpu/amd/agesa/s3_resume.h"
|
||||
#include "cbmem.h"
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627uhg/w83627uhg.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
#include <cbmem.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include <superio/nuvoton/nct5104d/nct5104d.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
u32 val, t32;
|
||||
u32 *addr32;
|
||||
|
||||
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
|
||||
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
|
||||
* even though the register is not documented in the Kabini BKDG.
|
||||
* Otherwise the serial output is bad code.
|
||||
*/
|
||||
//outb(0xD2, 0xcd6);
|
||||
//outb(0x00, 0xcd7);
|
||||
|
||||
amd_initmmio();
|
||||
|
||||
|
|
@ -65,27 +58,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
/* Enable the AcpiMmio space */
|
||||
outb(0x24, 0xcd6);
|
||||
outb(0x1, 0xcd7);
|
||||
outb(0x01, 0xcd7);
|
||||
|
||||
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
|
||||
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
|
||||
/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
|
||||
addr32 = (u32 *)0xfed80e28;
|
||||
t32 = *addr32;
|
||||
t32 &= 0xfff8ffff;
|
||||
t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
|
||||
t32 |= 0x00010000; // Set bit 16 for 25MHz
|
||||
*addr32 = t32;
|
||||
|
||||
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
|
||||
/* Enable Auxiliary OSCOUT1/OSCOUT2 */
|
||||
addr32 = (u32 *)0xfed80e40;
|
||||
t32 = *addr32;
|
||||
t32 &= 0xffffbffb;
|
||||
t32 &= 0xffffff7b; // clear 2, 7
|
||||
*addr32 = t32;
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
post_code(0x30);
|
||||
post_code(0x31);
|
||||
|
||||
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
nct5104d_enable_uartd(SERIAL_DEV);
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
}
|
||||
|
||||
|
|
@ -98,11 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
|
||||
int i;
|
||||
for(i = 0; i < 200000; i++)
|
||||
val = inb(0xcd6);
|
||||
|
||||
post_code(0x37);
|
||||
agesawrapper_amdinitreset();
|
||||
post_code(0x38);
|
||||
|
|
|
|||
Loading…
Reference in New Issue